industry news
Subscribe Now

DVCon U.S. 2021 Provides Outstanding Technical Program on Virtual Platform

Early registration is available through January 31

Gainesville, FL —January 21, 2021 —The 2021 Design and Verification Conference and Exhibition (DVCon) U.S. will be held on a virtual platform with a combination of recorded and live Q&A. The information-packed technical program runs four days and includes 42 papers, four tutorials, 14 posters, two panels, 18 short workshops and a keynote focused on computational logistics for system and software verification. Sponsored by Accellera Systems Initiative, DVCon U.S will be held March 1-4, 2021.

“Our technical program committee has worked very hard to put together an informative, highly technical program that I think attendees will find very valuable,” stated Vanessa Cooper, DVCon U.S. 2021 Technical Program Chair. “Holding the 33rd annual DVCon on a virtual platform gives us the opportunity to reach an even broader audience of design and verification engineers with topics such as UVM and RISC-V, functional safety, portable stimulus, machine learning, SystemC, low power design, formal verification to name just a few. I think our audience will benefit a great deal with the opportunity to experience even more of the program with the on-demand elements provided by a virtual platform.”

The program is now available online and an early registration rate is available through January 31. Registration for the keynote, panels and exhibits-only is free.

In addition to the 42 technical papers, program highlights include:

Monday, March 1

  • A tutorial, “Portable Stimulus 2.0 is Here: What You Need to Know” presented by members of Accellera’s Portable Stimulus Working Group.
  • 12 short workshops on Monday, including five presented by Accellera working groups and seven by sponsoring companies. Topics include functional safety, IP security, system-level power analysis, UVM-AMS, etc.

Tuesday, March 2

  • This year’s keynote, “Computational Logistics for System and Software Verification,” on Tuesday, March 2 from 1:00pm-2:15pm will be given by Dr. Paul Cunningham, corporate vice president and general manager of the system verification group at Cadence Design Systems, Inc. In his presentation, Dr. Cunningham will introduce the concept of verification throughput and highlight the significant opportunities we have as an industry to dramatically improve verification throughput on modern SoC designs.
  • 14 Posters will be presented from 10:30am-noon

Wednesday, March 3

  • There will be two panel sessions: “Verification in the Open-Source Era,” beginning at 8:30am and “Chip Design on Cloud – from Pipe Dream to Preeminence” beginning at 1:00pm. Both panels will offer attendees an opportunity to ask questions during a live Q&A.
  • The Best Paper and Best Poster presentation will be held at 4:45. Attendees are encouraged to cast their votes throughout the virtual conference.

Thursday, March 4

  • Three sponsored tutorials:
  1. “Benefits of a Common Methodology for Emulation and Prototyping,” sponsored by Cadence Design Systems
  2. “Applying Big Data to Next-Generation Coverage Analysis and Closure,” sponsored by Siemens EDA
  3. “Raising the Verification Bar: Cloud based Simulation Increases Verification Efficiency,” sponsored by Synopsys, Inc.
  • Six sponsored short workshops on topics such as RISC-V based SoC design, verification and debug; functional debug; accelerating sign-off; verification coverage from safety to certification; Cloud as a platform enabling faster verification; hardware-software co-design & co-verification using ESL methodologies

The interactive Expo will be open Tuesday from 2:00pm to 5:00pm, Wednesday from 2:00pm to 6:00pm and Thursday from 12:30pm to 1:30pm. During the Expo there will be networking opportunities to give attendees the ability to meet online with peers and experts in the design and verification community.

For the complete DVCon U.S. 2021 schedule, including the full list of tutorials, short workshops, panels, posters, and virtual events, visit the program agenda.

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit For more information about DVCon U.S., please visit Follow DVCon on Facebook or @dvcon_us on Twitter or to comment, please use #dvcon_us.

Leave a Reply

featured blogs
Mar 7, 2021 Made autonomously driving in San Francisco Monday: Update: Hogan, Mars, Australia, Solarwinds Tuesday: Cruising Through San Francisco with No Driver Wednesday:... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Mar 7, 2021
Join us as we celebrate Women in STEM as part of International Women's Day 2021, and see how diveristy, inclusion & equity form the heart of the Synopsys team. The post Celebrating International Women'€™s Day at Synopsys…Hands Up! appeared first on From Silicon ...
Mar 5, 2021
The combination of the figure and the moving sky in this diorama -- accompanied by the music -- is really rather tasty. Our cats and I could watch this for hours....
Mar 5, 2021
In February, we continued to build out the content on the website, released a new hierarchy for RF products, and added ways to find Samtec “Reserve” products. Here are the major web updates to for February 2021. Edge Card Content Page Samtec offers a fu...

featured paper

Use Configurable Digital IO To Give Your Industrial Controller the Edge

Sponsored by Maxim Integrated

As factories get bigger, centralized industrial process control has become difficult to manage. While there have been attempts to simplify the task, it remains unwieldy. In this design solution, we briefly review the centralized approach before looking at what potential changes edge computing will bring to the factory floor. We also show a digital IO IC that allows for smaller, more adaptable programmable logic controllers (PLCs) more suited to this developing architecture.

Click here to download the whitepaper

featured chalk talk

Time Sensitive Networking for Industrial Automation

Sponsored by Mouser Electronics and Intel

In control applications with strict deterministic requirements, such as those found in automotive and industrial domains, Time Sensitive Networking offers a way to send time-critical traffic over a standard Ethernet infrastructure. This enables the convergence of all traffic classes and multiple applications in one network. In this episode of Chalk Talk, Amelia Dalton chats with Josh Levine of Intel and Patrick Loschmidt of TTTech about standards, specifications, and capabilities of time-sensitive networking (TSN).

Click here for more information about Intel Cyclone® V FPGAs