industry news
Subscribe Now

ADLINK’s COM-HPC module powered by 13th Gen Intel® Core processor offers up to i9, 24 cores, and 36MB cache at 65W TDP

transcending cross-industry innovations with profound scalability, I/O bandwidth, and performance per watt

Summary:

  • The ADLINK COM-HPC-cRLS Client type Size C module based on 13th Gen Intel® Core™ processor is available for order with:
    • up to 13th Gen Intel® Core™ i9 processor, 16 Performance-cores, 8 Efficient-cores, and 32 threads
    • up to 128GB DDR5 SODIMM at 4000MT/s
      and 36MB cache (6MB more than predecessors)
    • 1 x16 PCIe Gen 5, 2x 2.5GbE LANs
  • Supporting Intel® TCC, and Time Sensitive Networking (TSN), COM-HPC-cRLS is well-suited for hard-real-time computing workloads required by applications such as industrial automation semiconductor equipment testing, and AI robots

Taipei, Taiwan – August 15, 2023

ADLINK Technology Inc., a global leader in edge computing, announces the readily availability of one of its most sought-after Computer-on-Modules based on the latest, 13th Gen Intel® Core™ processors — The COM-HPC-cRLS, a COM-HPC Client type Size C module.

Utilizing Intel’s advanced hybrid architecture, with up to 16 Performance-cores plus 8 Efficient-cores and an increased cache of 36MB, the module demonstrates brilliant performance per watt along with AVX-512 VNNI and Intel® UHD AI inferencing support for realizing diverse edge AI and IoT use cases.

Available with up to 13th Gen Intel® Core™ i9 processor at 65W TDP, the COM-HPC-cRLS provides two 2.5GbE LANs and up to 128GB DDR5 SODIMM at 4000MT/s. Most importantly, it packs 1 x16 PCIe Gen5 lanes that can fulfill the same computing and transmission performance with fewer lanes than its predecessors, and with a bandwidth of up to 32GT/s, in driving next-gen compute-intensive edge innovations.

What’s more, the module offers Intel® TCC (Time-Coordinated Computing) and TSN (Time Sensitive Networking) support. TCC brings precise time synchronization and CPU/IO timeliness within a system, whereas TSN optimizes time precision for synchronized networking between multiple systems. With these two features working coincide with one another, COM-HPC-cRLS can be assured of the timely execution of deterministic, hard real-time workloads with ultra-low latency, making it well fitted for hard real-time computing workloads required by applications such as industrial automation, semiconductor equipment testing, AI robots, autonomous driving, and aviation.

All in all, the ADLINK COM-HPC-cRLS cannot only simplify developers’ application-specific carrier designs and reduce their time to market significantly with PCIe Gen5 but also caters to various future-proof edge AI use cases at all fronts.

COM-HPC-cRLS

  • Up to 24 cores (16 P-cores + E-cores), 32 threads
  • 16 PCIe Gen5 lanes, 8 PCIe Gen4 lanes
  • Up to 128GB DDR5 SO-DIMM at 4000 MT/s
  • 2x 2.5GbE LANs
  • AI inferencing (AVX-512 VNNI, Intel® UHD)

ADLINK is also working to provide I-Pi development kits based on the ADLINK COM-HPC-cRLS module for on-the-spot prototyping and referencing.

For more information about the ADLINK COM-HPC-cRLS module, please follow the following link here at adlniktech.comCOM-HPC-cRLS (COM-HPC Client Type)

Leave a Reply

featured blogs
Dec 8, 2023
Read the technical brief to learn about Mixed-Order Mesh Curving using Cadence Fidelity Pointwise. When performing numerical simulations on complex systems, discretization schemes are necessary for the governing equations and geometry. In computational fluid dynamics (CFD) si...
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Universal Verification Methodology Coverage for Bluespec RISC-V Cores

Sponsored by Synopsys

This whitepaper explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solutions, and a RISC-V processor core from Bluespec.

Click to read more

featured chalk talk

Advancements in Motor Efficiency Enables More Sustainable Manufacturing
Climate change is encouraging the acceleration of sustainable and renewable manufacturing processes and practices and one way we can encourage sustainability in manufacturing is with the use of variable speed drive motor control. In this episode of Chalk Talk, Amelia Dalton chats with Maurizio Gavardoni and Naveen Dhull from Analog Devices about the wide ranging benefits of variable speed motors, the role that current feedback plays in variable speed motor control, and how precision measurement solutions for current feedback can lead to higher motor efficiency, energy saving and enhanced sustainability.
Oct 19, 2023
6,282 views