SAN JOSE, CA – March 22, 2011 — ATopTech, Inc., the leader in next generation physical design solutions, has completed compliance test of the company’s Aprisa place and route engine for TSMC’s 28nm process technology. The latest version of Aprisa is now qualified and ready for designs in TSMC’s 28nm process.  TSMC’s EDA qualification reports are available at TSMC-Online. 

TSMC extensively tested Aprisa to ensure its compliance with 28nm process requirements, including design rules and design for manufacturing (DFM) practices. The results meet TSMC’s accuracy and quality standards. Independent of TSMC’s tests, ATopTech has added additional functionality in Aprisa and Apogee, the company’s floor planning and chip assembly tool, in anticipation of 28nm design challenges. 

“Having ATopTech’s place and route tool qualified for TSMC’s 28nm process technology is an important milestone,” said Suk Lee, director of design infrastructure marketing at TSMC. ”We are pleased with the progress of ATopTech supporting TSMC 28nm technology.” 

“ATopTech’s P&R technology is architected specifically for design in advanced technology,” said Jue-Hsien Chern, CEO of ATopTech. “Qualifying for TSMC’s 28nm process technology reiterates our commitment to always delivering cutting-edge solutions to our customers.”

About ATopTech

ATopTech, Inc., is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com