In part 1 of this 3-part series, we talked about how you can save 75% on your next mixed-signal chip design – which was great, but we think we can do better than that. In this episode of Chalk TalkHD Amelia chats with Reid Wender of Triad Semiconductor about how you can dramatically reduce design costs and … Read More → "How To Save 99% on Your Next Mixed Signal ASIC Design (part 2 of a 3-part series)"
Do you think developing a custom mixed-signal chip for your application is beyond your team’s reach? Too expensive, complicated, and risky? Think again! In this episode of Chalk TalkHD Amelia chats with Reid Wender of Triad Semiconductor about how you can dramatically reduce design costs and complexity – bringing that custom chip design within reach. In part … Read More → "How To Save 75% on Your Next ASIC Design"
In this episode of Chalk TalkHD Amelia chats with Bob Potock (Kozio) about how you can save yourself a bunch of headache at prototype time and how Kozio’s VTOS (Verification and Test Operating System) can solve all of your embedded design prototyping problems. Click the link below to download the free whitepaper: Introducing VTOS for … Read More → "The Hardware Prototype Arrives — Find Design Errors Fast and Improve Design Quality"
Building a hybrid computing platform from scratch is a huge and complicated project. Luckily, somebody has already done that work for you. In this episode of Chalk Talk HD Amelia chats with Justin Braun (4DSP) about how you can use pre-designed platforms to dramatically simplify these complex computing and data acquisition problems. Click the link below to get more … Read More → "High Speed Data Acquisition and Software Defined Radio Made Simple"
Many of us have heard about the new game-changing devices that combine ARM-based SoCs with FPGA fabric. These are some of the most exciting devices to hit the market in the last decade. In this episode of Chalk TalkHD I chat with Todd Koelling of Altera about what’s inside these new SoC FPGAs and how … Read More → "Why Do I Need a Customizable ARM-based SoC?"
What if we could design our embedded devices in a way that pretty much took the battery issue off the table? If we could dramatically reduce our power consumption, the choice of battery wouldn’t be such a critical compromise in our design. And – what if – for some devices – we could get rid … Read More → "Maximizing Battery Life with TI’s Wolverine Technology"
Industrial Ethernet is one of the most important and widespread standards out there, but implementing high-performance ethernet can be tricky. Never fear, in this episode of Chalk TalkHD Amelia chats with Suhel Dhanani (Altera) about the who, what, and how of industrial ethernet design. Click here for more information about designing industrial ethernet with Altera and Softing. Click … Read More → "Simplifying Industrial Ethernet Design"
Getting the right power to your FPGA has gotten a lot more complicated, but it doesn’t have to mess up your day or cut into your golf time. In this episode of Chalk Talk HD Amelia chats with Jordon Inkeles (Altera) and Sharad Khanal (Linear Technology) about pairing Altera’s Stratix V FPGAs with Linear Technology’s power modules for … Read More → "Powering Stratix V FPGAs (Made Easy)"
Most FPGA designers don’t know much about formal methodologies for verification. It’s too bad, because today’s complicated FPGA designs can really take advantage of standardized methodologies like UVM. In this episode of Chalk TalkHD Amelia and Jerry Kaczynski (Aldec) are going to unscramble the anagrams and get you on your way to understanding and harnessing the power of … Read More → "Verification Methodologies (Made Easy)"
FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program one of these awesome FPGA+CPU … Read More → "OpenCL on FPGAs: Accelerating Performance and Design Productivity"
Jan 17, 2019
After two interesting blogs by Yagya Mishra that explained the most popular features of the Run Plan assistant in Virtuoso® ADE Assembler , I am writing this third blog in the series to share... [[ Click on the title to access the full blog on the Cadence Community site...
Jan 16, 2019
112 Gbps Samtec Flyover'¢ Demo Samtec's Ralph Page walks us through a live demonstration of a Samtec Flyover'¢ system which enables 112 Gbps PAM4 performance. The Credo CDR generates two ports of 31-bit PRBS data at 112 Gbps PAM4 data rates. The signal travels from...