chalk talk
Subscribe Now

Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution

 

5G presents daunting challenges for RF design. RF modules are reaching a level of complexity such that verification and analysis now demand about half of the design time, and that requires an integrated flow including physical verification and analysis as well as circuit design. In this episode of Chalk Talk, Amelia Dalton chats with Michael Thompson from Cadence Design Systems about how the Virtuoso RF Solution addresses the challenges of 5G RF design.

Click here for more information about the Cadence Design Systems Virtuoso RF Solution

Leave a Reply

featured blogs
Mar 18, 2019
My latest article on embedded.com has been published. This piece is the thirtieth installment of the RTOS Revealed series, which will continue to appear for the next few months. The series covers every aspect of real time operating systems. Nucleus SE RTOS initialization and ...
Mar 18, 2019
Today'€™s dense and complex PCB designs require realistic 3D view to investigate the design issues way before they are ready for manufacturing. The complexity of the PCB designs is increasing... [[ Click on the title to access the full blog on the Cadence Community site. ]...
Mar 15, 2019
Readers of the Samtec blog are familiar with the benefits of FMC and FMC+. These popular interfaces define a compact electro-mechanical expansion interface for a daughter card to an FPGA baseboard or other device with re-configurable I/O capability. VITA 57.1 has been around ...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...