editor's blog
Subscribe Now

Sticking With their Story: Zeno Demonstrates 1T SRAM at Leading Nodes

Let’s face it: We’re addicted to SRAM. It’s big, it’s power-hungry, but it’s fast. And no matter how much we complain about it, we still use it. Because we don’t have anything better in the mainstream yet.

We’ve looked at attempts to improve conventional SRAM. We’ve looked at completely different memory technologies that might be in line to replace SRAM, like RRAM (first more than five years ago, then last year – and we’re still working on it) and MRAM. And, a couple of years ago, we looked at one attempt to create a new SRAM technology out of conventional transistors – to be clear, just one such transistor (instead of six), plus a possible select transistor.

The company was Zeno, and they were even leveraging this idea as a way to provide greater drive in a transistor – possibly meaning one could stick with older technologies for longer. But, back in the memory story, there was at least one unknown – granted, a “we think so,” but without proof.

Here’s the thing: the original technology was proven on 28-nm planar technology. Could it be leveraged onto more aggressive nodes – ones with FinFETs? While Zeno thought it should work, they hadn’t run the experiments yet to prove it.

And it turns out that there was another nagging question – one of the little details that can sabotage a great new idea. The technology was originally implemented with a buried N-well below the transistor. This wasn’t – and isn’t – part of a standard CMOS flow. Yeah, it’s possible to change flows over time, but it’s super hard, and there better be a dang good payoff from it. Is a 1T SRAM cell enough to motivate that? Perhaps, but the other question to ask – and the one that Zeno asked – is, “Is that modification to the flow really necessary? What happens if we omit the buried N well. Will it still work?”

At this year’s IEDM, they came back and reported on those two items – both in a discussion and in a paper that they presented. And the answer to the two questions is: Yes.

The next figure shows the layout at 14 nm, with a 6T conventional SRAM on the left and their 1T version on the right.

(Image courtesy IEDM/Zeno)

They also showed the “profile” at 14 nm as compared to the original 28-nm planar version. Note both the use of a FinFET and the absence of the underlying n-well on the right. This latest rendition uses the standard foundry CMOS process.

(Image courtesy IEDM/Zeno)

They presented data showing the stability of the bistable element as data is read repeatedly, showing it sticks around – and that the read operation isn’t destructive.

(Image courtesy IEDM/Zeno)

And they presented lots more detail on reading and writing results in their paper. If you have access to the IEDM proceedings, look for, “A Bi-stable 1- /2-Transistor SRAM in 14 nm FinFET Technology for High Density / High Performance Embedded Applications.

 

More info:

Zeno

Leave a Reply

featured blogs
Jul 6, 2020
If you were in the possession of one of these bodacious beauties, what sorts of games and effects would you create using the little scamp?...
Jul 3, 2020
[From the last episode: We looked at CNNs for vision as well as other neural networks for other applications.] We'€™re going to take a quick detour into math today. For those of you that have done advanced math, this may be a review, or it might even seem to be talking down...
Jul 2, 2020
In June, we continued to upgrade several key pieces of content across the website, including more interactive product explorers on several pages and a homepage refresh. We also made a significant update to our product pages which allows logged-in users to see customer-specifi...

featured video

Product Update: What’s Hot in DesignWare® IP for PCIe® 5.0

Sponsored by Synopsys

Get the latest update on Synopsys' DesignWare Controller and PHY IP for PCIe 5.0 and how the low-latency, compact, power-efficient, and silicon-proven solution can enable your SoCs while reducing risk.

Click here for more information about DesignWare IP Solutions for PCI Express

Featured Paper

Cryptography: Fundamentals on the Modern Approach

Sponsored by Maxim Integrated

Learn about the fundamental concepts behind modern cryptography, including how symmetric and asymmetric keys work to achieve confidentiality, identification and authentication, integrity, and non-repudiation.

Click here to download the whitepaper

Featured Chalk Talk

Thermal Management Solutions

Sponsored by Mouser Electronics and Panasonic

With shrinking form factors, tighter power budgets, and higher performance, thermal management can be a challenge in today’s designs. It might be time to bust out the thermal grease to help conduct away some of that excess heat. But, before you grab that tube, check out this episode of Chalk Talk where Amelia Dalton chats with Len Metzger of Panasonic about the details, drawbacks, and design considerations when using thermal grease - and its alternatives.

Click here for more information about Panasonic Thermal Management Solutions