By John Ferguson – Mentor, A Siemens Business Do you really know what goes into a PDK? You might be amazed to learn where they came from, and where they’re headed next. John Ferguson provides his insights and opinions. Most IC designers ...
The latest release of Xpedition® Enterprise, VX.2.4, is now available for download! The VX.2.4 release provides innovative technologies that recognize the importance of achieving first-pass design success through Design Verification, from design capture through to manufacturing, improved library data management including accelerated ...
If you are in any way involved in the automotive supply chain or ecosystem, you have heard about functional safety and ISO 26262. ISO 26262 gives criteria for determining the degree of confidence required for any design tool or an entire toolchain and methodology (...
We are currently offering a program of free webinars covering a selection of embedded software topics: the Embedded Software Masterclass. These have been running for nearly a year, at approximately monthly intervals, and have proven quite popular. After the presentation segment, there ...
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Mentor Chalk Talks
Addressing Challenges with Large SerDes System Designs
The latest high-speed SerDes standards put high demands on PCB design. In this episode of Chalk Talk, Amelia Dalton chats with Cristian Filip of Mentor about best practices and tools you can apply to implementing and validating the SerDes design on your next circuit board.
Click here for more information about SerDes Channel Design and Analysis.
Click here to register for a seminar entitled “New Solutions for Large-Scale SerDes System Design and Verification.”
Via to Via Coupling Through Plane Cavities
Via to via crosstalk can be a challenging issue in PCB design, and there are a number of myths and misconceptions about how to best reduce it. In this episode of Chalk Talk, Amelia Dalton chats with Fadi Deek from Mentor about the physics behind via to via crosstalk and how to best mitigate it in your next board design.
Click here for more information about HyperLynx Power Integrity
Click here to download a whitepaper entitled “Concepts of Power Integrity: Taking the Noise out of Via-to-Via Coupling”
Integrating Schematic Integrity Analysis Into Any Design Flow
Schematic integrity problems cause a lot of expensive PCB re-spins. Errors in schematics can lead to schedule delays, manufacturing reruns, support problems, and higher overall project costs. In this episode of Chalk Talk, Amelia Dalton chats with Craig Armenti from Mentor about how Xpedition Schematic Integrity Analysis can help catch and correct errors in your PCB schematics right when they happen.
Click here for more information Schematic Integrity Analysis
Click here to download a whitepaper called “Is There a More Efficient Solution for SERDES Channel Analysis (or Design)?”