“Any other questions?” asked my optometrist. “Yes. We live in the 21st century. My prescription corrects to better than 20/20, but can I get some upgrades? How do I get the same visual acuity as an eagle looking for a mouse from high ...
The answer is YES! These days, nearly every designer deals with some degree of signal integrity constraints, both to maximize design performance and to stay on top in today’s competitive and fast-paced technology market. Nowadays, independent engineers and small teams do ...
Next Friday – 13 July – I am participating in a joint seminar with Doulos, looking in detail at the use of C in embedded applications. We will be considering why it is so popular and appropriate, and taking a detailed look at some best ...
Achieving Clean Design Early with Calibre-RTD The Darker Side Of Consolidation Not All Emulators Are Created Equal EDA learns to love AI Mentor Graphics Backs Functional Safety Bet with Austemper Design Systems Achieving Clean Design Early with Calibre-RTD SemiWiki Traditional IC physical ...
Mentor on Facebook
Mentor on Twitter
Mentor Chalk Talks
Addressing Challenges with Large SerDes System Designs
The latest high-speed SerDes standards put high demands on PCB design. In this episode of Chalk Talk, Amelia Dalton chats with Cristian Filip of Mentor about best practices and tools you can apply to implementing and validating the SerDes design on your next circuit board.
Click here for more information about SerDes Channel Design and Analysis.
Click here to register for a seminar entitled “New Solutions for Large-Scale SerDes System Design and Verification.”
Via to Via Coupling Through Plane Cavities
Via to via crosstalk can be a challenging issue in PCB design, and there are a number of myths and misconceptions about how to best reduce it. In this episode of Chalk Talk, Amelia Dalton chats with Fadi Deek from Mentor about the physics behind via to via crosstalk and how to best mitigate it in your next board design.
Click here for more information about HyperLynx Power Integrity
Click here to download a whitepaper entitled “Concepts of Power Integrity: Taking the Noise out of Via-to-Via Coupling”
Integrating Schematic Integrity Analysis Into Any Design Flow
Schematic integrity problems cause a lot of expensive PCB re-spins. Errors in schematics can lead to schedule delays, manufacturing reruns, support problems, and higher overall project costs. In this episode of Chalk Talk, Amelia Dalton chats with Craig Armenti from Mentor about how Xpedition Schematic Integrity Analysis can help catch and correct errors in your PCB schematics right when they happen.
Click here for more information Schematic Integrity Analysis
Click here to download a whitepaper called “Is There a More Efficient Solution for SERDES Channel Analysis (or Design)?”