https://youtu.be/O1r7cqyVm90 I was on China24 on CGTNAmerica earlier this week, being interviewed about the Chinese Semiconductor Industry. www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email. Virtuosity: What's New in Run Plan – Part II
I wrote about new enhancements in Virtuoso® ADE Assembler Run Plan feature in Part I . This blog is continuing on the same topic concentrating on additional enhancements added since IC6.1.7 ISR15. How can I see all my Results at Once? If you’...
I don't normally write about the FPGA market. There are three reasons for this. First, Cadence doesn't participate in the market for FPGA tools (for FPGA users. I'm pretty sure the arrays themselves are almost all designed on Virtuoso). ...
At CDNLive EMEA Robert Schweiger laid out his perspective on the automotive market. At April’s CDNLive Silicon Valley too, but as you might guess from his name, Germany is his home. Sanjay Lall, the head of Cadence EMEA, had told me ...
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In-Design DFM Accelerates New Product Design and Introduction Process
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Mixed-Signal Digital Complexity Explosion
Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems.
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Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP
Neural networks are taking over a broad range of exciting applications these days. But, the amount of computation required for neural network inferencing can be daunting. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai of Cadence Design Systems about some new processor IP designed specifically for neural network inferencing.
Click here for more information about Tensilica Vision DSPs for Imaging, Computer Vision, and Neural Networks