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Less Pessimism, Please

POCV is the Latest Salvo in Improving Timing Analysis Accuracy

by Bryon Moyer

When I was a teen, I remember someone coming to help my Dad plan a big move of some piece of equipment on our orchard. What struck me was how this guy could pre-visualize all the various scenarios and then consider the consequences and, in particular, all the things that could possibly go wrong for the different cases.

I was pretty impressed. It seemed like such thorough analytical capabilities were a skill and a gift. Over time, however, I’ve noticed that such an ability isn’t always appreciated. Because most of the world likes to assume best-case conditions, the “value add” of the more thorough approach is to point out that there are potential negative consequences too. Which makes you Mr. Negative. The pessimist. Always there to dash cold water on a hot idea. Doesn’t matter if you’re right.  Read More


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The Process of Process Tracking

Satin Attempts to Corral a Recalcitrant Beast

by Bryon Moyer

Breaking the System

Good Pieces Don’t Always Make a Good Whole

by Bryon Moyer

Let's Get Small

Smaller Chips, Smaller RTOS, Smaller Shows

by Jim Turley

Design West 2012 Shakedown

by Amelia Dalton


 

 

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Max 10 Kills the CPLD

Posted on 10/01/14 at 3:12 AM by juergenuk

juergenuk
@Steve DevKits are mostly subsidized, so does not count. I meant designed in, product cost, how does it compare Altera - Lattice - Microsemi - Xilinx imlementation ( sorry if I forgot some ). I know there are many variants - any example/volume appreciat…

Expanding EDA

Posted on 09/30/14 at 10:10 PM by Kev

Given that the EDA guys are a rather non-"Agile" bunch I'm not sure they're going to get much done.

Personally I think you can re-apply a lot of EDA tools aimed at hardware design at parallel software design. Parallel stuff is hard to debug, so formal …

Max 10 Kills the CPLD

Posted on 09/30/14 at 11:38 AM by SteveCasselman

@juergenuk You can buy a development board with the largest part for $50. The smallest part is 25 times smaller and yet is still large enough to fit a NIOS processor and 16 DSP units plus logic left over.

Max 10 Kills the CPLD

Posted on 09/30/14 at 11:10 AM by juergenuk

juergenuk
I am missing where this new Altera series fits price wise. Lattice never went to the biggest - but instead a market not so much served by A and X. I have been selling against A and X - or more positively, finding the right niches for Lattice.
So Lattice …

Expanding EDA

Posted on 09/29/14 at 9:57 AM by bmoyer

bmoyer
What do you think about the cycles of EDA and EDA's expanding scope?

Who Controls the Power?

Posted on 09/29/14 at 2:11 AM by GuidoGam

Not a single word about Alpha?

There’s a Processor in My FPGA!

Posted on 09/28/14 at 10:35 PM by JohnSwan

JohnSwan
Indeed, Mentor Graphics had the ASAP (Application Specific Assistant Processor)tool 10 years ago. It automated the ability for the user to select a function and push it onto the FPGA fabric. It used an HLS tool of course for the synthesis. Though OpenCL g…

The Four Horsemen

Posted on 09/25/14 at 12:05 PM by Dick Selwood

Dick Selwood
Are we just muddling along? Are we about to stall?

IoT Standards

Posted on 09/22/14 at 5:19 PM by bmoyer

bmoyer
Thanks for the link, Will. I'll look into it.

Tiny Diamonds

Posted on 09/22/14 at 9:50 AM by bmoyer

bmoyer
What do you think about using ultra-nano-crystalline diamond as an actuator?

Welcome to the beta version of EE Journal's new product section.  When you start designing something awesome and need information on specific components, we want EEJournal to be your go-to resource. If you have an idea that would make this section more useful in your next design project, Let us know, and we'll get working on it.


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