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Max 10 Kills the CPLD

@Steve DevKits are mostly subsidized, so does not count. I meant designed in, product cost, how does it compare Altera - Lattice - Microsemi - Xilinx imlementation ( sorry if I forgot some ). I know there are many variants - any example/volume appreciat…

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Expanding EDA

Given that the EDA guys are a rather non-"Agile" bunch I'm not sure they're going to get much done.

Personally I think you can re-apply a lot of EDA tools aimed at hardware design at parallel software design. Parallel stuff is hard to debug, so formal …

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Who Controls the Power?

Not a single word about Alpha?

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There’s a Processor in My FPGA!

Indeed, Mentor Graphics had the ASAP (Application Specific Assistant Processor)tool 10 years ago. It automated the ability for the user to select a function and push it onto the FPGA fabric. It used an HLS tool of course for the synthesis. Though OpenCL g…

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The Four Horsemen

Are we just muddling along? Are we about to stall?

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IoT Standards

Thanks for the link, Will. I'll look into it.

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Tiny Diamonds

What do you think about using ultra-nano-crystalline diamond as an actuator?

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Differentiation versus Diversity

Hi Jim, nice to see your very positive comments about Tilera’s architecture and performance achievements. And we've got over 100 designs at companies like Cisco, Brocade, ZTE, Checkpoint who agree with that. But it’s worth correcting a couple statement…

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Be a Better Programmer

Programmers put the bugs in. So they should get help where possible with tools and training to minimize. One way is to have a very rigid structure across the whole group.
On LinkedIN there was an interesting discussion, and some said: I want my programmi…

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Go-Fast FPGA Design

I'd add "Make room for heatsinks." Especially if you're packing the whole FPGA with logic and cranking up the clock, you will need help taking the heat from the chip. I've never regretted allowing extra room for a big heatsink, including board-level mou…

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