industry news
Subscribe Now

Plunify Launches Latest Version of InTime with Timing Optimization in the Cloud

Will Demonstrate InTime, Plunify Cloud Platform at Design Automation Conference

SINGAPORE –– June 21, 2018 –– Plunify®, a leading design optimization technology provider, will launch the latest version of InTime™  at the Design Automation Conference (DAC) next week, offering on-demand development, optimization, testing and deployment of field programmable gate array (FPGA) designs.  

The latest version of InTime will introduce post-placement estimates analysis and support multiple concurrent compilations in the cloud to meet design performance targets, reducing runtime and costs. A new Plunify Cloud plugin capability for the Xilinx Vivado® Design Suite enables users to optimize their designs directly in the cloud if local resources and licenses aren’t sufficient.

Plunify’s timing closure experts will demonstrate InTime and the Plunify Cloud platform in its Booth (#2124) during DAC June 25-27 at the Moscone Center in San Francisco.

InTime, the first tool to address an FPGA’s timing and performance using a unique machine learning approach, analyzes past compilation results to predict optimal synthesis/place-and-route parameters and placement locations to solve critical design problems and improve timing performance.

It runs on the user’s servers or in a cloud computing environment. Using InTime with the cloud providers such as Amazon Web Services (AWS),   harnesses cloud computing’s value to solve IT bottlenecks such as scaling and provisioning at a competitive cost. It also delivers better quality of results with less turnaround time, especially for heavily congested designs.

Availability and Pricing

InTime is shipping now. Pricing is available upon request.

Plunify has sales managers in Australia, China, India, Japan, Singapore and the United States with a variety of customer service options including on-site training, hotline support and consulting services.

About Plunify

Solutions from Plunify enable designers to meet FPGA design performance targets, shorten product time to market and reduce development costs with no disruption to existing workflows. It solves complex chip design timing and performance problems through machine learning techniques for a variety of markets. Those include communications, data center applications and applications such as high-end test and measurement equipment, advanced driver assistance systems (ADAS) and high-frequency trading (HFT). Plunify’s portfolio includes the Plunify Cloud™ and EDAxtend™ chip design platforms, InTime timing closure tool and InTime Service.

Engage with Plunify at:

Website: www.plunify.com

Twitter: @plunify

LinkedIn: http://www.linkedin.com/company/plunify

Facebook: https://www.facebook.com/Plunify

Plunify’s blog: http://blog.plunify.com

Leave a Reply

featured blogs
Jul 17, 2018
In the first installment, I wrote about why I had to visit Japan in 1983, and the semiconductor stuff I did there. Today, it's all the other stuff. Japanese Food When I went on this first trip to Japan, Japanese food was not common in the US (and had been non-existent in...
Jul 16, 2018
Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA'€™s configuration bits. Each Speedcore instance contains its own FPGA configu...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...