Embedded Systems Conference, Boston, MA – September 20 2010. LDRA (Booth 414), the leading provider of automated software verification, source code analysis and test tools, has integrated the LDRA tool suite with a variety of compiler and RTOS technologies for the PowerPC (PPC) family. Targeting safety-critical systems, LDRA has extended its PPC support across the primary tool chains of Wind River Tornado, Wind River Workbench … Read More → "LDRA Tool Suite High- and Object-Level Support Extended for Full Range of PowerPCs"
Firefly Design Group Teams Up with D-Tools to Provide Data and Consulting Services for System Integrator™ Software Users
CONCORD, CA, SEPTEMBER 16, 2010 – D-Tools, Inc., the worldwide leader in system integration software, today announced that system integration consulting firm Firefly Design Group has joined the D-Tools Certified Partner Program to provide services around D-Tools award-winning System Integrator software. Firefly Design Group provides marketing, system design, project documentation, data and package creation, and best practices for D-Tools SI users.
“We’re tremendously pleased to become a D-Tools Certified Partner and to be able to help custom integrators improve their business through the use of the D-Tools software platform,” said Ron Callis, Founder … Read More → "Firefly Design Group Teams Up with D-Tools to Provide Data and Consulting Services for System Integrator™ Software Users"
SANTA CLARA, Calif., September 15, 2010 –
Who: MoSys (NASDAQ: MOSY), a leading provider of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, is exhibiting at GSA’s Emerging Opportunities Expo and Conference on September 16, 2010. MoSys will be located in booth 503.
Tanner EDA Joins IPL Alliance to Widen Adoption of Interoperable Process Design Kits for Analog/ Mixed-signal Designs
MONROVIA, California – September 14, 2010 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), has joined the IPL Alliance, an industry organization established to develop an interoperable eco-system for custom design by creating and promoting interoperable process design kit (iPDK) standards. Tanner EDA provides analog and mixed-signal (A/MS) designers with the Read More → "Tanner EDA Joins IPL Alliance to Widen Adoption of Interoperable Process Design Kits for Analog/ Mixed-signal Designs"
Eindhoven, The Netherlands, September 14, 2010. Huntron, Inc., a leader in PCB diagnosis and troubleshooting equipment for over 30 years, and JTAG Technologies, a tier one supplier of boundary-scan products world-wide, today announced the integration of their test methods within Huntron’s range of prober enhanced analog signature analysis products.
‘Huntron Tracker’ is synonymous with PCB fault detection using the technique known as analog signature analysis. From today users of this technology can now take advantage of advancements made in the digital world that allow PCBs to be tested using built-in logic … Read More → "Boundary-scan Boost for Huntron Robotic Probers"
MOUNTAIN VIEW, Calif., Sept. 14 /PRNewswire/ — Synopsys, Inc. (NASDAQ: SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that eMemory Technology, Inc. has selected Synopsys’ CustomSim(TM) solution for all of its circuit simulation needs. On a 45-nanometer (nm) embedded non-volatile memory, the CustomSim solution demonstrated up to 2 times faster simulation runtime compared to other commercial FastSPICE tools, and delivered results tightly correlated to silicon data. Based on these results, CustomSim is now used in verification … Read More → "eMemory Standardizes on Synopsys FastSPICE for Circuit Simulation"
Synopsys Showcases DesignWare IP Solutions for PCI Express, USB and SATA at Intel Developer Forum 2010
SAN FRANCISCO, Sept. 10 /PRNewswire/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, will be demonstrating its complete DesignWare® IP solutions for PCI Express® 3.0, USB 3.0 and SATA 6 Gb/s, consisting of device, host, PHY and verification IP, at the Intel Developer Forum (IDF) in San Francisco, California from September 13-15.
IDF is the premier global technology industry event bringing together technology professionals who are actively directing where technology is going. … Read More → "Synopsys Showcases DesignWare IP Solutions for PCI Express, USB and SATA at Intel Developer Forum 2010"
Northwich, Cheshire, 2nd September 2010. Kane Computing Ltd (KCL), today announced that the popular Impulse C to FPGA tool set, that they sell in the UK has now been integrated to Stone Ridge Technology products. The integration enables software developers to write HLL (High Level Language) signal, imaging or data processing algorithms that rapidly compile to optimized … Read More → "C-to-FPGA Integration Accelerates DSP Prototyping by ten"
CEVA’s New 1 GHz Programmable DSP Core Offers Exceptional Performance and Power Efficiency for Next Generation Communications and Multimedia SoCs
MOUNTAIN VIEW, Calif. – September 07, 2010 – CEVA, Inc. [(NASDAQ: CEVA); (LSE: CVA)], the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today introduced the CEVA-X1643™, a highly-energy efficient,1 GHz DSP core designed to boost overall chip performance for a broad range of applications including wireline and wireless communications, surveillance, portable multimedia and more. The CEVA-X1643 is the latest family member of the widely used CEVA-X DSP architecture, which has been licensed by more than 25 customers and shipped in over 100 million devices to … Read More → "CEVA’s New 1 GHz Programmable DSP Core Offers Exceptional Performance and Power Efficiency for Next Generation Communications and Multimedia SoCs"
Oslo, Norway, September 2, 2010 – Energy Micro®, the energy efficient microcontroller company, has introduced a free software tool designed to remove the traditionally time-consuming problem of debugging I/O pin conflicts. Supporting the complete EFM32 Gecko low power MCU family, energyAware Designer ensures correct pin configuration and automatically generates set-up code and documentation.
On creating a new project, designers select a target MCU and are presented with a default device configuration. Clicking on a peripheral function enables it and highlights respective pins in green on an intuitive pin-out diagram. Pin-conflicts induced by selecting another peripheral, … Read More → "Energy Micro tool instantly resolves MCU pin conflicts"