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ASTER announces the first DfT software to combine Electrical and Mechanical analysis

Cesson-Sévigné,  France, March 2010 — During APEX 2010 at the New Mandalay Bay Resort & Convention Center in Las Vegas, ASTER Technologies, the leading supplier in Board-Level Testability and Test Coverage analysis tools, will introduce the first Design for Test (DfT) software to combine electrical and mechanical analysis.

It has been developed to address a new vision of the DfT market that has to solve the many challenges that developers face today, such as: shrinking release cycles, budget compression and improvement in product quality.

TestWay, the world-wide reference … Read More → "ASTER announces the first DfT software to combine Electrical and Mechanical analysis"

Geotest and Pickering Interfaces Announce Strategic Alliance

IRVINE, CA AND CLACTON-ON-SEA, ESSEX, ENGLAND, March 2010 — In an effort to enhance customer’s choices and options when designing PXI systems,  Geotest- Marvin Test Systems, a global producer of PXI and PC-Based test equipment and test solutions, and Pickering Interfaces, a global market innovator in signal switching and conditioning,  announced today that they are embarking on a Strategic Alliance program.

An initial element of this program has been the creation of a joint web site, www.PXI4test.com, designed to educate … Read More → "Geotest and Pickering Interfaces Announce Strategic Alliance"

EXFO Extends Its Market-Leading OTN Test Capabilities to 100G Ethernet Testing

QUEBEC CITY, March 17 /PRNewswire-FirstCall/ — EXFO Inc. (NASDAQ:EXFO) (NASDAQ: TSX:) (NASDAQ:EXF) announced today the addition of optical transport network (OTN) testing capabilities on its FTB/IQS-85100G Packet Blazer 100G/40G Ethernet Test Modules. These include OTU4 (111.81 Gbit/s) and OTU3 (43.018 Gbit/s) full-line-rate testing, as … Read More → "EXFO Extends Its Market-Leading OTN Test Capabilities to 100G Ethernet Testing"

New UK Distributor for Impulse C to FPGA Compiler

8th March, 2010, Northwich, Cheshire – Kane Computing Ltd (KCL) today announced the signing of an agreement with Impulse Accelerated Technologies (Impulse) to resell their software-to-hardware FPGA compilation and verification tools in the UK and Ireland.

The Impulse C-to-FPGA tools allow application developers to quickly create custom accelerator and filter modules in C, increasing productivity for developers of advanced video and image processing, DSP, and hardware-accelerated computing applications. Users of Impulse C report saving as much as half their design time using C when compared to using HDL methods.

Products and services KCL will be supporting include … Read More → "New UK Distributor for Impulse C to FPGA Compiler"

Saelig Debuts New features for Low-cost Oscilloscope

Pittsford, NY, USA:  Saelig Company, Inc. announces new features for the PDS5022S low-cost, full-featured 25MHz two-channel benchtop oscilloscope. The new features are: Auto-scale, FFT, and trigger hold, normally found on much more expensive instruments. 

  • Autoscale can be set to automatically adjust the vertical gain, or the horizontal time base, or both together.  This is useful for circuit probing — as the probe is moved from point to point on a circuit board, the display auto-adjusts for best trace presentation.  It functions in … Read More → "Saelig Debuts New features for Low-cost Oscilloscope"

Agilent Technologies to Display Latest Wireless Test Solutions at CTIA WIRELESS 2010

SANTA CLARA, Calif., March 9, 2010 — Agilent Technologies Inc. (NYSE: A) today announced it will demonstrate the latest wireless test and measurement solutions at CTIA WIRELESS 2010, March 23-25, Las Vegas Convention Center, Booth 2427. Agilent’s test solutions address the latest wireless technologies, including LTE, TD-LTE, 3GPP W-CDMA, HSPA+, E-EDGE (EDGE Evolution), UMA/GAN, WiMAX™, and femtocells.

CTIA WIRELESS 2010 is the premier event for all things wireless. While testing mobile devices, diagnosing infrastructure, and optimizing networks are hidden from consumers, they are critical success factors for wireless manufacturers and operators. Helping the wireless industry deal with the most advanced … Read More → "Agilent Technologies to Display Latest Wireless Test Solutions at CTIA WIRELESS 2010"

Synopsys Galaxy Custom Designer Accelerates Analog/Mixed-Signal Engineering Productivity with Built-in DRC Visualization and Correction

MOUNTAIN VIEW, Calif., March 9, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that it has enhanced its Galaxy Custom Designer(TM) solution with the addition of SmartDRD, an innovative design-rules-driven technology. SmartDRD technology enables layout engineers to more quickly achieve design-rule-check (DRC) clean designs with significantly reduced effort for analogue and custom designs. SmartDRD automates many DRC repair tasks, reducing hours of manual effort to mere seconds.

Driven by the need to manage increasing design complexity and ever-growing design rule counts and their interrelationships, SmartDRD … Read More → "Synopsys Galaxy Custom Designer Accelerates Analog/Mixed-Signal Engineering Productivity with Built-in DRC Visualization and Correction"

Imec and Synopsys collaborate on 3D stacked IC development

MOUNTAIN VIEW, Calif. – March 9, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and the Belgian nanoelectronics research center, imec, today announced they have entered into a collaboration to use Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools for characterising and optimising the reliability and electrical performance of through-silicon vias (TSVs). The collaboration will accelerate the development of 3D stacked IC technologies.

While considered an emerging technology, 3D stacked IC complements conventional transistor scaling and allows multiple chips to be stacked and integrated into a single package. … Read More → "Imec and Synopsys collaborate on 3D stacked IC development"

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