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Synopsys chosen by Realtek as its primary EDA partner

MOUNTAIN VIEW, Calif., Nov. 5, 2009 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Realtek Semiconductor Corp, a leading provider of advanced IC products for communications network, computer peripheral and multimedia applications, has signed an expanded business agreement establishing Synopsys as its primary EDA partner. Under the new multi-year agreement, Realtek has extended its use of Synopsys’ Galaxy(tm) Implementation, Discovery(tm) Verification and Confirma(tm) Rapid Prototyping Platforms, as well as Synopsys’ DesignWare(r) IP and consulting services.

“By selecting Synopsys as … Read More → "Synopsys chosen by Realtek as its primary EDA partner"

Infineon and TSMC Extend Technology And Production Partnership Agreement; Will Jointly Develop 65nm Embedded Flash Process Technology For Automotive and Chip Card Applications

NEUBIBERG, Germany and HSINCHU, Taiwan, R.O.C., Nov. 5 /PRNewswire-FirstCall/ — Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) and Taiwan Semiconductor Manufacturing Company (TWSE: 2330, NYSE: TSM) today announced that they are extending their development and production partnership to a 65nanometer (nm) embedded flash (eFlash) process technology targeting next generation automotive, chip card and security applications. Based on the agreement, Infineon and TSMC will jointly develop 65nm process technologies for eFlash microcontrollers (MCUs) that fulfill the stringent quality requirements of the automotive industry, as well as the demanding security requirements of the chip card and security markets.

The … Read More → "Infineon and TSMC Extend Technology And Production Partnership Agreement; Will Jointly Develop 65nm Embedded Flash Process Technology For Automotive and Chip Card Applications"

Digi-Key Corporation Launches Digi-Key Toolbar Version 2

Redesign based on customer feedback includes new customization features

Thief River Falls, Minnesota (USA) — November 5, 2009 — Electronic components distributor Digi-Key Corporation, recognized by design engineers as having the industry’s broadest selection of electronic components available for immediate shipment, today announced the launching of a newly redesigned version of its toolbar.

Redesigned with busy design engineers, purchasers, and electronic enthusiasts in mind, the new version of Digi-Key’s Toolbar allows for additional customization. Features include quick access to each of Digi-Key’s 25 country-specific websites and eight language options, giving the user the ability … Read More → "Digi-Key Corporation Launches Digi-Key Toolbar Version 2"

Agilent Technologies Introduces Compact USB 3.0 Test Setup

Agilent Will Demonstrate Setup at USB-IF Compliance Workshop

SANTA CLARA, Calif., Nov. 2, 2009 — Agilent Technologies Inc. (NYSE: A) today announced it significantly enhanced its SuperSpeed USB test solution portfolio with the introduction of new test fixtures and the support of automated compliance tests and characterization with the new J-BERT N4903B. The new, compact setup will be unveiled at the USB-IF Compliance Workshop in Portland, Ore., Nov. 2-4.

USB 3.0 is an update of the well-established, widespread standard driven by USB Implementers Forum, Inc., a non-profit corporation founded by the group of companies that developed the … Read More → "Agilent Technologies Introduces Compact USB 3.0 Test Setup"

Synopsys TetraMAX ATPG cuts test development schedule at Arrow Electronics

Multicore processing speeds runtime by 3X, accelerates time-to-quality

MOUNTAIN VIEW, Calif., November 3, 2009 – Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Arrow Electronics successfully deployed Synopsys’ TetraMAX(R) automatic test pattern generation (ATPG) with multicore processing to significantly reduce the time needed to generate high quality manufacturing tests. Stringent quality goals combined with increasing design complexity stimulated the need to improve ATPG performance at Arrow. By utilising TetraMAX ATPG’s multicore processing capability on their quad-core compute servers, Arrow’s Custom Logic … Read More → "Synopsys TetraMAX ATPG cuts test development schedule at Arrow Electronics"

PLDA: Wintegra Incorporates PCI Express® IP in its WinPath3 Processors

PLDA’s quality design and Ease of migration from legacy PCI to PCI Express interface delivers the right blend of features for Wintegra’s third generation WinPath devices

SAN JOSE, Calif.–(BUSINESS WIRE)–PLDA, the industry leader in the high-speed bus IP market, announced that Wintegra has chosen PLDA’s PCI Express IP for their latest WinPath3 processor. Wintegra, a leading provider of high performance connectivity solutions for wireless and wireline infrastructure applications, is utilizing PLDA’s PCI Express IP to provide PCI Express interconnect within its host controller, helping to enable … Read More → "PLDA: Wintegra Incorporates PCI Express® IP in its WinPath3 Processors"

Juniper Networks Completes World’s First Network Instruction Set Processor Design Using Mentor Graphics Calibre and Design-for-Test Solutions

WILSONVILLE, Ore., November 3, 2009 – Mentor Graphics Corporation (NASDAQ: MENT) today announced that Juniper Networks has completed the world’s first network instruction set processor IC using Mentor Graphics® physical verification and silicon test tools.

Juniper’s new processor is part of Juniper’s latest Junos® Trio chipset that enables the delivery of Juniper’s MX-3D platforms. “We went with the Calibre® verification platform because it gives a high level of confidence in the manufacturability of our design,” said Debashis Basu, senior director of Foundation Technologies at … Read More → "Juniper Networks Completes World’s First Network Instruction Set Processor Design Using Mentor Graphics Calibre and Design-for-Test Solutions"

EDA Solutions announces Tanner process design kit support for X-FAB’s 0.18µm technologies

Fareham, UK: EDA Solutions announces that X-FAB has released two 0.18µm process design kits (PDK) for Tanner Tools Pro on X-TIC, X-FAB’s online technical database. Tanner Tools Pro is the software suite for the design, layout and verification of analog, mixed-signal (A/MS), RF and MEMS ICs from Tanner EDA, the world leader in PC-based A/MS and MEMS circuit design software. The release of this new kit extends X-FAB’s PDK support for Tanner tools, adding X-FAB’s 0.18µm processes to the range of technologies currently supported (0.35, 0.6, 0.8 and 1.0µm). The new PDK will … Read More → "EDA Solutions announces Tanner process design kit support for X-FAB’s 0.18µm technologies"

HDL Design House Announces I2S Soft Core

Belgrade, Serbia – November 3rd, 2009 – HDL Design House has announced I2S soft IP core(HIP 3700). HIP 3700 I2S soft IP core is based on a generic, highly modular architecture from which a variety of solutions can be easily created to effectively and efficiently address customers’ specific requirements. I2S is an audio transmission standard, used to connect system elements such as Analog to Digital and Digital to Analog converters, speakers or audio subsystems. HIP 3700 is silicon proven I2S Controller IP Core compliant with the Philips* Inter-IC Sound specification. IP Core provides up to 8 audio … Read More → "HDL Design House Announces I2S Soft Core"

Synopsys extends DFTMAX compression to reduce the cost of pin-limited test

Delivers predictable high compression with only one pair of test data pins

MOUNTAIN VIEW, Calif., November 2, 2009 — Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced a new capability in DFTMAX(tm) compression that significantly reduces the cost of test for designs and methodologies that mandate very few test pins. Extending Synopsys’ patented adaptive scan technology with a high-performance, low-pin interface to the tester allows designers to achieve predictable compression of up to 100X or more with only one pair of test data pins. As designers … Read More → "Synopsys extends DFTMAX compression to reduce the cost of pin-limited test"

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