industry news
Subscribe to EE Journal Daily Newsletter
2 + 8 =

Mentor Ushers in New Era of C++ Verification Signoff with New Catapult Tools and Solutions

  • New Catapult DesignChecks tool finds bugs early in C++/SystemC HLS code requiring no testbench – saving designers days or weeks of debugging.
  • New Catapult Coverage provides synthesis-aware RTL-like coverage metrics of C++/SystemC HLS code – for fast, easy coverage closure from C to RTL.
  • New C to RTL Equivalence SLEC HLS tool formally verifies Catapult HLS C++/SystemC source to synthesized RTL – providing ultimate verification confidence from C to RTL.
  • Catapult HLS now generates a complete UVM environment for synthesized RTL – saving weeks/months in RTL testbench creation for blocks and SoC.

Mentor, a Siemens business, today announced three new tools – Catapult® Coverage, Catapult Design Checks and SLEC® HLS – and enhancements to Catapult HLS. These new tools and enhancements further strengthen Mentor’s High-Level Synthesis (HLS) tool portfolio, which enables logic chip designers to cut project schedules by over 50 percent for applications such as machine vision, machine learning, high-performance telecommunications, video, and image processing. The new tools and enhancements bring register-transfer level (RTL)-quality verification and methodologies to the C-language level, enabling chip architects and designers to design and verify in C++/SystemC more quickly with added confidence.

“We are excited to be at the forefront of HLS innovation and driving the next-generation ecosystem,” said Badru Agarwala, general manager, Calypto Systems Division at Mentor. “An increasing number of customers are moving from RTL to HLS as a key competitive advantage, because it enables complex designs with late-changing specifications to cut project schedules in half or do twice as much with the same resources. This milestone of C++ verification signoff deliverables now makes it even easier for RTL designers and system architects to move to HLS with confidence.”

Catapult DesignChecks

The new Catapult DesignChecks tool helps users quickly and easily find bugs as they are coding, saving debug time in simulation and synthesis. Catapult DesignChecks has two modes; a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. Both modes support C++ and SystemC and focus on hardware- oriented checks such as out-of-bounds reads/writes and uninitialized memory reads that are difficult to find in simulation. Catapult DesignChecks is easy to use and requires no testbench.

Catapult Coverage

The new Catapult Coverage tool allows users to accurately measure code coverage for C++ signoff and fast closure of synthesized RTL. Unlike other tools that measure coverage on C/C++, Catapult Coverage is synthesis-aware. This means that it accurately reports coverage for HLS use-cases (such as loop-unrolling, function inlining, and bit-accurate datatypes), which is very important so that results match the structural coverage of the RTL with no additional user effort. It supports line, branch, statement and (soon) expression coverage. It also automatically generates Mentor’s unified coverage database (UCDB), giving users RTL-quality coverage metrics and analysis tools using the Questa Verification Management suite.


The new C-to-RTL-Equivalence SLEC (sequential logic equivalence checking) HLS tool formally verifies C++/SystemC source to Catapult-synthesized RTL, dramatically reducing or eliminating the need for design teams to perform simulation/verification of RTL. Design teams have used the SLEC family of tools in production for over 10 years for C-to-RTL formal equivalence with a manual setup. SLEC HLS is a new addition that Mentor has tightly integrated with Catapult HLS to generate an automatic setup, enabling the fastest possible path for verification. It avoids the “all or nothing” problem often found in formal equivalence by employing a coverage methodology that highlights exactly which code still needs to be tested if a full proof could not be achieved. SLEC HLS enables designers to have the ultimate confidence to move to high-level synthesis.

UVM Framework Generation

Catapult can now automatically generate a complete ready-to-use universal verification methodology (UVM) environment using the UVM Framework. This provides the RTL and system-on-chip (SoC) verification teams with a complete verification environment for the synthesized RTL that is easily modifiable and still has all of the power of UVM with constrained random, re-use of C tests and the HLS C model as a predictor. Teams can use this environment as-is for block verification or in a higher level UVM environment for sub-system/SoC verification.

Mentor will be demonstrating the new Catapult tools at the Design Automation Conference on June 19-21st in Austin, TX. Visit booth #947.

Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world’s most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Web site:

Leave a Reply

featured blogs
Dec 12, 2017
The latest semi-annual RISC-V workshop took place the week after Thanksgiving. The last one was in Shanghai. The next one is in Barcelona. This one was in...Milpitas. At least it didn't require a plane to get there. It was at what I think of as SanDisk, but has been West...
Dec 12, 2017
Samtec is expanding its line of ExaMAX® high speed backplane connectors. The new system is a direct mate orthogonal (DMO) configuration. These products were recently on display at SC17 in Denver. In the video above, Jonathan Sprigler, Samtec’s Backplane Product Manager...
Nov 16, 2017
“Mommy, Daddy … Why is the sky blue?” As you scramble for an answer that lies somewhere between a discussion of refraction in gasses and “Oh, look—a doggie!” you already know the response to whatever you say will be a horrifyingly sincere “B...
Nov 07, 2017
Given that the industry is beginning to reach the limits of what can physically and economically be achieved through further shrinkage of process geometries, reducing feature size and increasing transistor counts is no longer achieving the same result it once did. Instead the...