industry news
Subscribe Now

Matrox Imaging Unveils Rapixo CXP Series Frame Grabbers at The Vision Show 2018

Multi-link frame grabbers support the highest speeds in CoaXPress 2.0 for high-end machine vision applications

Montreal — 9 April 2018 — Matrox® Imaging is pleased to announce Matrox Rapixo CXP, a new series of multi-link CoaXPress 2.0 frame grabbers. Leveraging the latest version of CoaXPress®, the Rapixo CXP boards support data rates of up to four times 12.5 Gbps, with a PCIe® x8 host computer interface to match, as required in high-speed, high-resolution machine vision applications. Rapixo CXP features up to four connections, and further simplifies integration with support for Power-over-CoaXPress (PoCXP) that combines power, command, and data interfaces onto one cable. Matrox Rapixo CXP boards also offer custom onboard image processing using their field-programmable gate array device (FPGA) and can also host the license for Matrox Imaging software, avoiding the need for a separate hardware key.

Watch Video: Significance of CoaXPress 2.0 and Matrox Rapixo CXP – Q&A with Matrox
 Imaging
www.matrox.com/imaging/RapixoCXP

Key features:

Higher speed with CXP 2.0
The major feature of the CoaXPress 2.0 standard is the increased data rate; now to up to 12.5 Gbps. The doubled bandwidth per connection is thoroughly ready for the new generation of high-resolution high-rate image sensors.

Simplified connection
Rapixo CXP supports up to four connections to either interface with up to four CXP 2.0-compliant cameras or to accommodate higher data rates from one or two cameras through connection aggregation. The PoCXP design streamlines system set up by combining the camera’s power interface with its command- and data-interface onto the same coaxial cable.

Custom FPGA-based image processing
Rapixo CXP makes use of a FPGA device from the Xilinx Kintex® UltraScale™ family for not only integrating the control, formatting, and streaming logic of the various interfaces, but also allowing developers to incorporate Matrox Imaging- or user-developed custom image pre-processing operationsdeveloped in C/C++to offload from the host computer.

Supported by Matrox Imaging Library (MIL) software
Applications using the Rapixo CXP are programmed using the latest MIL software development kit (SDK) and can target either 64-bit Windows® or Linux®. The frame grabber series also facilitates application deployment through an integrated license fingerprint for MIL software.

“The Matrox Rapixo CXP family provides immediate benefits and access to customers looking to leverage the CoaXpress 2.0 standard,” says Mathieu Larouche, product manager, Matrox Imaging. “The added speed over a single link looks to be a boon for interfacing to cameras that will integrate a new generation of still higher-resolution and higher-rate sensors in the most straightforward way.”

Availability
The Matrox Rapixo CXP will be available in Q2 2018.

Visit Matrox Imaging at The Vision Show (April 10-12, 2018; booth 1003) for the introduction of the Matrox Rapixo CXP.

About Matrox Imaging
Matrox Imaging is an established and trusted supplier to top OEMs and integrators involved in machine vision, image analysis, and medical imaging industries. The components consist of smart cameras, vision controllers, I/O cards, and frame grabbers, all designed to provide optimum price-performance within a common software environment. For more information, visit www.matrox.com/imaging.

Leave a Reply

featured blogs
Aug 17, 2018
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the compa...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...