industry news
Subscribe Now

Leti Silicon Photonics Design Kit Available for Synopsys Optodesigner PIC Design Solution

Kit Contains Design Rules and Building Blocks for Multi-Project Wafers And Custom Runs on Leti’s Si310 Platform

GRENOBLE, France – April 5, 2018 – Leti, a research institute of CEA Tech, today announced Leti’s silicon photonics process design kit (PDK) for photonic circuits is available in the Synopsys PhoeniX OptoDesigner suite.

Leti’s integrated silicon photonics platform has been developed for high-speed optical transceivers and highly-integrated optical interposer applications. The process design kit contains the design rules and building blocks for multi-project wafer and custom runs on Leti’s Si310 platform. It also includes a catalogue of components available at Leti, allowing Synopsys PhoeniX OptoDesigner customers to select the ones they need to build their circuits. Once the customers have a completed circuit design, Leti produces a proof of concept on a multi-project wafer run.

Used by more than 300 designers worldwide, OptoDesigner gives access to a complete set of passive components, such as grating couplers, silicon waveguides and transitions; and active components, such as high-speed Mach Zehnder modulators and high-speed germanium photodiodes based on Leti’s fab. It also includes physical verification tools checking whether the contributions meet the design rules defined by the fabrication constraints in Leti’s clean room.

“On the same mask, with this design kit, we are able to have photonic circuits performing various functions, according to the area of expertise of the different contributors,” said Andre Myko, responsible of MPW runs at Leti. “Fabless companies and academics therefore can realize substantial cost savings by ‘sharing’ production costs on multi-project wafer runs.”

Leti is a world leader in silicon photonics technology. Its photonic platform is France’s largest R&D center for the development, characterization and simulation of optoelectronic systems and components. Its activities range from component design through component fabrication, integration into systems and packaging.

“Leti’s process design kit available for Synopsys’ PhoeniX OptoDesigner is a licensed plug-in library of solutions that support multi-project wafers and custom runs provided by Leti,” said Niek Nijenhuis, global business development manager of Synopsys’ PhoeniX OptoDesigner products. “In addition to the photonic elements from the standard OptoDesigner library, Leti’s PDK contains technology-specific information like mask layer names, design rules, validated building blocks, die sizes and GDS file settings.”

Leti’s silicon photonics platform is also fully compatible with STMicroelectronics’ platform in Crolles, which enables fabless customers to take their new circuits to high-volume production.

About Leti

Leti, a technology research institute at CEA Tech, is a global leader in miniaturization technologies enabling smart, energy-efficient and secure solutions for industry. Founded in 1967, Leti pioneers micro-& nanotechnologies, tailoring differentiating applicative solutions for global companies, SMEs and startups. Leti tackles critical challenges in healthcare, energy and digital migration. From sensors to data processing and computing solutions, Leti’s multidisciplinary teams deliver solid expertise, leveraging world-class pre-industrialization facilities. With a staff of more than 1,900, a portfolio of 2,700 patents, 91,500 sq. ft. of cleanroom space and a clear IP policy, the institute is based in Grenoble, France, and has offices in Silicon Valley and Tokyo. Leti has launched 60 startups and is a member of the Carnot Institutes network. Follow us on www.leti-cea.com and @CEA_Leti.

CEA Tech is the technology research branch of the French Alternative Energies and Atomic Energy Commission (CEA), a key player in innovative R&D, defence & security, nuclear energy, technological research for industry and fundamental science, identified by Thomson Reuters as the second most innovative research organization in the world. CEA Tech leverages a unique innovation-driven culture and unrivalled expertise to develop and disseminate new technologies for industry, helping to create high-end products and provide a competitive edge.

Leave a Reply

featured blogs
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....
Apr 18, 2024
Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. V...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

SLM Silicon.da Introduction
Sponsored by Synopsys
In this episode of Chalk Talk, Amelia Dalton and Guy Cortez from Synopsys investigate how Synopsys’ Silicon.da platform can increase engineering productivity and silicon efficiency while providing the tool scalability needed for today’s semiconductor designs. They also walk through the steps involved in a SLM workflow and examine how this open and extensible platform can help you avoid pitfalls in each step of your next IC design.
Dec 6, 2023
17,866 views