industry news
Subscribe Now

Leti and Mapper Develop Individualized Chips with Maskless Lithography in CMOS Process

Low-Cost Cyber-Security Breakthrough that Encrypts Individual Chips With a Unique Code Presented at SPIE Advanced Lithography 2018 in San Jose

GRENOBLE, France and DELFT, Netherlands – March 2, 2018 – Leti, a research institute of CEA Tech, and Mapper Lithography, the leading provider of maskless lithography equipment for the semiconductor and nanofabrication industries, today announced a low-cost cyber-security breakthrough that encrypts individual chips with a code.

The non-falsifiable code is generated by using a unique chip design that leverages direct multi-beam writing in a process that fits in a conventional CMOS flow with an extra level of lithography and without photomasks. Throughput on Mapper‘sFLX-1200 tool installed at Leti is compatible with optical systems.

The markets for these chips include data security, traceability and combatting imports of counterfeit chips.

Leti, a specialist in electron-beam lithography, and Mapper, a Dutch company, presented a paper on the breakthrough, “Process development of a maskless N40 via level for security application with multi-beam lithography”, today at SPIE Advanced Lithography 2018 in San Jose, Calif. The paper demonstrates a via patterning integration that is compliant with standard CMOS 40nm process flow.

“Standard optical exposure tools – optical scanners using masks – repeat the identical design on the entire silicon wafer, and cannot fabricate individualized chips,” said Leti’s Isabelle Servin, the lead author of the paper. “Leti applied its deep multi-beam lithography knowhow and Mapper‘s unique maskless fabrication tools to achieve this differentiating, cyber-security chip.”

The maskless lithography system, based on massively parallel electron-beam writing capability developed by Mapper, is designed for high-volume specialty chips and low-volume advanced logic.

Leti and Mapper are demonstrating the breakthrough for their customers at Leti’s facility in Grenoble.

About Mapper

Mapper, based in Delft, The Netherlands, is developing a groundbreaking maskless lithography infrastructure for the semiconductor and nanofabrication industry. The capabilities of a maskless patterning system with 65,000 electron beams enable unique functionalities in high volume nanofabrication and specialized logic. Typical examples are security and identification chips and integrated optics functionalities on image sensors for smart phones. Mapper employs 270 people.

For further information, please visit mapper.nl

About Leti

Leti, a technology research institute at CEA Tech, is a global leader in miniaturization technologies enabling smart, energy-efficient and secure solutions for industry. Founded in 1967, Leti pioneers micro-& nanotechnologies, tailoring differentiating applicative solutions for global companies, SMEs and startups. Leti tackles critical challenges in healthcare, energy and digital migration. From sensors to data processing and computing solutions, Leti’s multidisciplinary teams deliver solid expertise, leveraging world-class pre-industrialization facilities. With a staff of more than 1,900, a portfolio of 2,700 patents, 91,500 sq. ft. of cleanroom space and a clear IP policy, the institute is based in Grenoble, France, and has offices in Silicon Valley and Tokyo. Leti has launched 60 startups and is a member of the Carnot Institutes network. Follow us on www.leti-cea.com and @CEA_Leti.

Leave a Reply

featured blogs
Jun 22, 2018
A myriad of mechanical and electrical specifications must be considered when selecting the best connector system for your design. An incomplete, first-pass list of considerations include the type of termination, available footprint space, processing and operating temperature...
Jun 22, 2018
You can't finish the board before the schematic, but you want it done pretty much right away, before marketing changes their minds again!...
Jun 22, 2018
Last time I worked for Cadence in the early 2000s, Adriaan Ligtenberg ran methodology services and, in particular, something we called Virtual CAD. The idea of Virtual CAD was to allow companies to outsource their CAD group to Cadence. In effect, we would be the CAD group for...
Jun 7, 2018
If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn'€™t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors '€” then progressing to gates, ALUs...
May 24, 2018
Amazon has apparently had an Echo hiccup of the sort that would give customers bad dreams. It sent a random conversation to a random contact. A couple had installed numerous Alexa-enabled devices in the home. At some point, they had a conversation '€“ as couples are wont to...