industry news
Subscribe to EE Journal Daily Newsletter
1 + 1 =

Imec Achieves Record Low Contact Resistivity on Ga-doped Ge Source/Drain Contacts for pMOS Transistors

LEUVEN, Belgium—Dec. 4, 2017 – At this week’s 2017 International Electron Devices Meeting (IEDM), imec, the world-leading research and innovation hub in nanoelectronics and digital technology, reports ultralow contact resistivity of 5×10-10Ωcm2 on Gallium (Ga)-doped p-Germanium (Ge) source/drain contacts. The low contact resistivity and high level of Ga activation were achieved after nanosecond laser activation (NLA) at low thermal budget. The results show that highly Ga-doped Ge-rich source/drain contacts provide a promising route for suppressing parasitic source/drain resistance in advanced pMOS devices.

These  breakthrough results are important in light of further downscaling of the CMOS source/drain contact area, which is challenged by a parasitic source/drain resistance and results in suboptimal transistor functioning. High dopant activation is known to be an attractive approach for lowering source/drain contact resistance. Traditionally in pMOS devices, Silicon (Si) source/drain contacts with high boron (B) activation are used. But in more advanced pMOS devices, Ge- and SiGe(Sn)-based source/drain are a promising alternative since they introduce beneficial strain. However, the higher the Ge content, the lower the boron activation and solubility in Ge or Ge-rich SiGe.

The new findings result from a comprehensive study of Ga dopant activation in Si, Si0.4Ge0.6 and Ge conducted by imec, KU Leuven (Belgium) and Fudan University (Shangai, China). In this study, either rapid thermal annealing (RTA) or Applied Materials’ nanosecond laser activation (NLA) were used as dopant activation technologies, after Ga ion implantation. A record low contact resistivity of 5×10-10Ωcm2 and a high dopant activation level of 5x1020cm-3 were obtained for Ga-doped Ge source/drain contacts after NLA. The low contact resistivity can be attributed to a beneficial Ge/Ga surface aggregation following the NLA process. With RTA activation at 400°C, a contact resistivity as low as 1.2×10-9Ωcm2 was reported. The study shows that Ga might be preferred over B as a dopant for Ge or high-Ge content source/drain contacts in pMOS devices.

“For the first time, we have achieved contact resistivities far below 10-9Ωcm2 for high-Ge content source/drain contacts,” said Naoto Horiguchi, distinguished member of the technical staff at imec. “This proves that Ga doping and activation by NLA or RTA are an attractive alternative to boron doping for these source/drain contacts. It provides a possible path for further performance improvement using the current source/drain schemes in next-generation technology nodes.”

The results were obtained at low thermal budget activation, making Ga doping particularly attractive for devices that require low-thermal budget processing.

Imec’s research into advanced logic scaling is performed in cooperation with key CMOS program  partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, SanDisk/Western Digital, Sony Semiconductor Solutions, TOSHIBA Memory and TSMC.

Leave a Reply

featured blogs
Jan 16, 2018
The Sunday of IEDM is always two full-day short courses. One is on the future of memory technology, one is on the future of logic technology. This year the logic one was titled Boosting Performance, Ensuring Reliability, Managing Variation in Sub-5nm CMOS . I have to admit I ...
Jan 16, 2018
Samtec will be introducing several new products at DesignCon 2018. All of these products are designed to increase data rates, increase system density, and shrink product footprints, so designers can meet their system signal integrity needs. NovaRay™ High Bandwidth, High ...
Jan 5, 2018
When visitors to CES 2018 want to travel to the Las Vegas Convention Center across town, it will likely be in a fully autonomous vehicle from Lyft getting them there. While this futurist trip will certainly be a first for many riders, this type of point-to-point travel will s...
Jan 10, 2018
Recently, Electronics Products Magazine announced their 42nd Annual Product of the Year award winners, with Cadence Design Systems winning for their Virtuoso® System Design Platform. According to the article, the editors “have chosen [products] they......
Jan 15, 2018
This is the seventh in a series of blog posts showcasing the winning designs from the 27th Annual PCB Technology Leadership Awards. The 1st place winner in the Telecom, Network Controllers & Line Cards  category is Altice Labs, Portugal. This Switching Matrix card is a...