Santa Clara, Calif., June 13, 2017 – GLOBALFOUNDRIES today announced the availability of its 7nm Leading-Performance (7LP) FinFET semiconductor technology, delivering a 40 percent generational performance boost to meet the needs of applications such as premium mobile processors, cloud servers and networking infrastructure. Design kits are available now, and the first customer products based on 7LP are expected to launch in the first half of 2018, with volume production ramping in the second half of 2018.
In September 2016, GF announced plans to develop its own 7nm FinFET technology leveraging the company’s unmatched heritage of manufacturing high-performance chips. Thanks to additional improvements at both the transistor and process levels, the 7LP technology is exceeding initial performance targets and expected to deliver greater than 40 percent more processing power and twice the area scaling than the previous 14nm FinFET technology. The technology is now ready for customer designs at the company’s leading-edge Fab 8 facility in Saratoga County, N.Y.
“Our 7nm FinFET technology development is on track and we are seeing strong customer traction, with multiple product tapeouts planned in 2018,” said Gregg Bartlett, senior vice president of the CMOS Business Unit at GF. “And, while driving to commercialize 7nm, we are actively developing next-generation technologies at 5nm and beyond to ensure our customers have access to a world-class roadmap at the leading edge.”
GF also continues to invest in research and development for next-generation technology nodes. In close collaboration with its partners IBM and Samsung, the company announced a 7nm test chip in 2015, followed by the recent announcement of the industry’s first demonstration of a functioning 5nm chip using silicon nanosheet transistors. GF is exploring a range of new transistor architectures to enable its customers to deliver the next era of connected intelligence.
GF’s 7nm FinFET technology leverages the company’s volume manufacturing experience with its 14nm FinFET technology, which began production in early 2016 at Fab 8. Since then, the company has delivered “first-time-right” designs for a broad range of customers.
To accelerate the 7LP production ramp, GF is investing in new process equipment capabilities, including the addition of the first two EUV lithography tools in the second half of this year. The initial production ramp of 7LP will be based on an optical lithography approach, with migration to EUV lithography when the technology is ready for volume manufacturing.
“We are very pleased with the leading-edge technology that GF is bringing with its advanced 7nm process technology. Our collaborative work with GF is focused on creating high-performance products that will drive more immersive and instinctive computing experiences.”
Mark Papermaster, CTO and senior vice president of technology and engineering, AMD
“While not the only important factor in a successful technology, transistor geometry still plays a part. This is an important fab milestone on the journey to 7nm volume production, demonstrating that GF’s process is mature enough to start working on real customer product designs. At the same time, the company is already making solid progress toward delivering 5nm and beyond. There are only a handful of companies in the world capable of driving this type of leading-edge innovation, and GF is clearly staking its claim as a member of this elite group.”
Patrick Moorhead, President & Principal Analyst, Moor Insights & Strategy
“GF continues to demonstrate America’s leadership in advanced technology. If they continue this progress on 7nm, GF will be the first company to leapfrog a full node. Everyone that’s tried it in the past has failed well before this point in the process. It’s a completely new strategic approach for extracting value from Moore’s Law. By biting the bullet and skipping 10nm, GF opened up the technical bandwidth to attack 7nm head-on. Others have been dividing their resources and going for half- or even quarter-nodes.”
Dan Hutcheson, CEO and Chairman of VLSI Research