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eSilicon at the AI Hardware Summit, September 18-19, 2018

10 percent discount available: use code ESILICON10 at registration

eSilicon, an independent provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will exhibit at the upcoming AI Hardware Summit. eSilicon will provide updates on its 7nm neuASIC™ platform, a modular methodology for machine learning ASIC design.

In addition, Patrick Soheili, eSilicon’s VP, business and corporate development, will participate on the autonomous driving panel on September 19.

In partnership with Kisaco Research, eSilicon is pleased to offer a 10 percent discount. Use code ESILICON10 at registration.

What:
neuASIC AI ASIC platform
Through customized, targeted IP offered in 7nm FinFET technology and a modular design methodology, eSilicon’s neuASIC platform makes AI ASICs possible, despite changing AI algorithms. The platform includes a library of AI-targeted functions that can be quickly combined and configured to create custom AI algorithm accelerators. eSilicon-developed and third-party IP can be configured as AI “tiles,” allowing early power, performance and area (PPA) analysis of various candidate architectures.

When:
Tuesday-Wednesday, September 18-19, 2018

Where:
Computer History Museum, Mountain View, California

About the AI Hardware Summit
The AI Hardware Summit is the first and only conference dedicated solely to the ecosystem developing hardware accelerators for neural networks and computer vision.

Join 250+ senior technology leaders from AI chip start-ups, semiconductor companies, system vendors/OEMs, data centers, end users, financial services, investors and fund managers, to build a comprehensive architectural roadmap of the emerging AI chip market.

Sample AI Hardware Summit Speakers

  • ARM
  • Cerebras
  • DeePhi
  • eSilicon
  • Facebook
  • Google Brain
  • Graphcore
  • GyrFalcon
  • IBM
  • Intel AI
  • M12 (Microsoft Ventures)
  • Mythic
  • Wave Computing
  • And many more…

About eSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC+IP synergies include highly configurable silicon-proven 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms that include HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets.

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