Henderson, NV – July 19th, 2018 – Aldec, Inc., an industry leader in Electronic Design Verification, has expanded the rule-checking capabilities of its popular ALINT-PRO™ tool in response to increasing verification challenges for complex, large-scale FPGA and ASIC designs. These enhanced capabilities include twice as many FSM checks and new graphical representations to aid state exploration.
“Most issues designers face when implementing FSM-based control blocks tend to be caught during RTL-signoff, using coverage-enabled simulation and/or formal property checking methods,”observes Sergei Zaychenko, Aldec Software Product Manager. “Aldec ALINT-PRO can discover many complex FSM issues long before test stimuli are available. With the latest version of ALINT-PRO™ users can do FSM-level verifications that will save them a significant amount of verification time further on down the line.”
Another major benefit to users through the 2018.07 release of ALINT-PRO™ is enhanced setup automation for complex Xilinx Vivado and ISE projects. The extension enables a “push button” flow for early static verification of IP-intensive Xilinx FPGA-targeted designs. A workspace is automatically organized to deliver hierarchical and incremental DRC and CDC analysis, allowing the designer to concentrate on checking custom RTL blocks, while preserving accuracy at the boundaries of IP blocks. Unless an IP block is re-configured in the original design environment it is only being analyzed once, and the extracted block-level timing constraints are automatically promoted to enable higher level verification of the main design.
ALINT-PRO 2018.07 Highlights
- Enhanced graphical representations to facilitate the better exploration of the extracted FSMs and reveal FSM-based design issues
- 25 new FSM design rules covering advanced aspects and typical errors
- More than 40 new rules to improve VHDL and Verilog/SystemVerilog RTL coding quality
- Greatly simplified initial setup for Xilinx Vivado/ISE complex IP-based designs
- Hierarchical and Incremental analysis for Out-of-Context (OoC) style Vivado IP blocks
- Support of physically and logically exclusive clock groups
- Introduced basics of multi-mode CDC analysis in simultaneous and case-based modes
- Multi-variant design rule checking settings via Project Configurations
About ALINT-PRO
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, reliable and portable FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC/RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically.
The 2018.07 release of ALINT-PRO includes numerous new features, usability enhancements, and performance optimizations.
For additional information, tutorials, free evaluation download and What’s New Presentation, visit https://www.aldec.com/Products/ALINT-PRO.
About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Emulation/Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, High-Performance Computing and Military/Aerospace solutions. www.aldec.com
