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DVCon U.S. 2018 Announces Call for Extended Abstracts & Panel Proposals

Submission site is open

Louisville, CO – July 27, 2017 — The 2018 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, is now accepting extended abstract and panel proposals for its conference to be held February 26-March 1, 2018 at the DoubleTree Hotel in San Jose, California.

“DVCon U.S., now in its 30th year, continues to be the ‘must-attend’ conference for practicing design and verification engineers and engineering management,” stated Dennis Brophy, DVCon U.S. 2018 General Chair.  “The DVCon U.S. Steering Committee crafts the industry’s most compelling technical program from solicited ideas on conference panels, papers, poster sessions, tutorials and workshops.  It brings EDA tool suppliers and users together to share practical information and methods that can be immediately applied to their electronic system design and verification challenges.”

Extended abstracts are being solicited for presentations that are highly technical and reflect real-life experiences and emerging trends in various domains such as:  Verification & Validation; Safety-Critical Design & Verification; Machine Learning and Big Data; Design & Verification Reuse and Automation; Mixed-Signal Design & Verification; and Low-Power Design & Verification.  Extended abstracts should be between 600-1200 words.  Deadline for submissions is August 8, 2017. More information and guidelines can be found here.

Two focused panel discussions will also be showcased at DVCon U.S.  The Panel Chair is looking for panel proposals that are lively, controversial, and provoke engaging discussion on a specific topic of interest to the audience.  Suggested topics include:  Experiences using design and/or verification IP for SoC development; design and verification sign-off and closure; dealing with the technical and logistical challenges of multi-site projects; experiences deploying a verification methodology library, especially the deployment of UVM; and designing and/or verifying complex ASICs and FPGAs using multiple HDLs and/or HVLs in a design cycle.  Deadline for panel proposals is September 29, 2017.  More information and guidelines can be found here.

About DVCon 

DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits.  DVCon is sponsored by Accellera Systems Initiative, an industry consortium dedicated to the development and standardization of design and verification languages. DVCon currently has four conferences around the globe: DVCon U.S., DVCon ChinaDVCon India and DVCon Europe.  Follow @dvcon on Twitter or to comment, please use #dvcon.

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