industry news
Subscribe Now

Cadence Shortens Automotive Verification Closure with New Verification IP for UFS 3.0, CoaxPress, and HyperRAM

Three VIP offerings enable designers to quickly achieve compliance with the latest protocols
SAN JOSE, Calif., May 3, 2018—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced three new Verification IP (VIP) offerings: the industry’s first CoaXPress VIP offering for high-speed imaging, the industry’s first HyperRAM high-speed memory VIP offering, and a VIP offering for the new JEDEC Universal Flash Storage (UFS) 3.0 specification. All three enable early adopters of these standards to begin designing with the new specifications immediately, ensuring compliance with the standard and achieving the fastest path to IP and system-on-chip (SoC) verification closure.
For more information on the new Cadence® VIP offerings, please visit
“Designers of SoCs for automotive applications face unique challenges of sustainability and reliability together with growing real-time processing needs that drive interfaces and memory standards innovation” said Michal Siwinski, vice president of product engineering and management, System and Verification Group at Cadence. “These three new VIP offerings add to the total Cadence Verification Suite to help engineers easily achieve compliance with the latest standards for rapid high-quality design of innovative new automotive electronics.”
VIP for UFS 3.0
The UFS 3.0 specification doubles the throughput bandwidth from 1333MB/s in UFS 2.1 to 2666MB/s in UFS3.0 to address the growing bandwidth, low power and responsiveness requirements of advanced automotive and mobile designs. The UFS 3.0 Memory Model provides a full-stack solution, including support for MIPI® Unified Protocol (UniProSM) 1.8 and MIPI M-PHYSM 4.1, with comprehensive coverage model and test suite. This VIP offering also utilizes Cadence TripleCheck technology for fast testing of all requirements for the specification.
“With the continuous evolution of memory specifications and the growing complexity of the protocols, early users of new standards need access to memory models that ease adoption,” said G.J. Perdaems, Senior Director of Managed NAND Solutions at Micron. “Our team is already utilizing the Cadence UFS Memory Model successfully, and it’s encouraging to see Cadence continue its commitment to develop first-to-market solutions for the latest protocols. With the Cadence Memory Model for UFS 3.0, our engineers can confidently verify our designs with ease so they can keep their focus on designing managed memory solutions and delivering products to market faster.”
VIP for CoaXPress
The CoaXPress interface standard provides high-speed serial communication over coaxial cable. It is ideal for automated acquisition and analysis of video and images, which is becoming more important as engineers develop autonomous driving applications. It also can be used in other industrial and machine vision applications requiring transfer speeds up to 6.25Gbit/s. It utilizes Cadence TripleCheck technology, which provides a verification plan with measurable objectives linked to the specification features and a comprehensive test suite with thousands of ready-to-run tests to ensure support for the specification.
VIP for HyperRAM
HyperRAM is a high-performance 333MB/sec read performance memory based on the HyperBus interface. It is ideal for applications that focus on a small footprint, including automotive, industrial and consumer applications.
These VIP offerings join the extensive Cadence VIP library, which provides a comprehensive portfolio for automotive applications including LPDDR 4/5, Ethernet TSN, MIPI CSI-2SM, DSI-2SM and I3CSM, DisplayPort, CAN and eMMC.
These VIP offerings are part of the Cadence Verification Suite and are optimized for Xcelium™ Parallel Logic Simulation, along with supported third-party simulators. They support the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.
About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine’s 100 Best Companies to Work For. Learn more at http://www.cadence.com.

 

Leave a Reply

featured blogs
Aug 17, 2018
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the compa...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...