industry news
Subscribe Now

Cadence Prototypes First IP Interface in Silicon for Preliminary Version of DDR5 Standard Being Developed in JEDEC

Test chip fabricated in TSMC 7nm process achieves 4400MT/sec data rate

SAN JOSE, Calif., May 1, 2018—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it has prototyped its first IP interface in silicon for a preliminary version of the DDR5 standard being developed in JEDEC. The Cadence test chip was fabricated in TSMC’s 7nm process and achieves a 4400 megatransfers per second (MT/sec) data rate, which is 37.5 percent faster than the fastest commercial DDR4 memory at 3200MT/sec. With this key milestone, SoC providers developing high-speed memory subsystems for high-end server, storage and enterprise applications can start developing their DDR5 memory subsystems now with silicon-tested PHY and controller IP from Cadence. For more information, please visit: www.cadence.com/go/ddr5iptestchip.

“TSMC recognizes the importance of next-generation DRAM for our enterprise and data center customers,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. “We’re pleased Cadence has proven interoperability with prototype DDR5 memory devices in our industry-leading 7nm process. This demonstrates a path to higher bandwidth and density for future server and storage devices manufactured at TSMC.”

“As part of Cadence’s DDR PHY validation and interoperability program, Micron has provided Cadence with engineering prototypes of the first memory for a preliminary version of the DDR5 standard,” said Ryan Baxter, director of Data Center segment, Compute and Networking Business Unit, at Micron. “We are enthusiastic that Cadence’s DDR5 IP test chip is able to interoperate consistently with our DDR5 prototype memory devices at the 4400MT/sec speed.”

“Cadence has taken a huge leap forward in enabling servers, storage and enterprise equipment with next-generation high-speed memory. Systems that use DDR5 will be able to achieve higher bandwidth than DDR4 while also using less power per bit transferred, enabling these systems to do more computing on larger data sets than what’s possible with DDR4,” said Babu Mandava, senior vice president and general manager, IP Group at Cadence. “Cadence next-generation DDR IP is ready for implementation now, and we look forward to enabling DDR5 SoC designs.”

Cadence is ready to engage with customers immediately to start SoC designs integrating DDR5 memory interfaces.

About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine’s 100 Best Companies to Work For. Learn more at cadence.com

© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Press contacts:

Cadence Design Systems GmbH
Andrea Huse
Tel: +49 (0) 89 4563 1726
Email: ahuse@cadence.com

Publitek
Oliver Davies/Janice Fenton
Tel: +44 (0) 1225 470000
Email: oliver.davies@publitek.com

Leave a Reply

featured blogs
Aug 17, 2018
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the compa...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...