industry news
Subscribe Now

Cadence Perspec System Verifier Supports New Accellera Portable Test and Stimulus Specification 1.0

Automates complex automotive, mobile and server SoC coverage closure and improves system-level test productivity by up to 10X
SAN FRANCISCO—DESIGN AUTOMATION CONFERENCE, June 26, 2018 — —Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the Cadence® Perspec™ System Verifier supports the new Accellera Portable Test and Stimulus Specification (PSS) 1.0 released by the Accellera Systems Initiative. The Accellera PSS enables a single representation of system-on-chip (SoC) tests and coverage metrics for hardware and software verification, creating efficiencies for design engineers. Through Cadence’s support for the standard, customers creating complex automotive, mobile and server designs can confidently adopt the Perspec System Verifier to automate SoC coverage closure and achieve up to 10X improved system-level test productivity.
The Perspec System Verifier provides an abstract model-based approach for defining the SoC use cases from the PSS model and uses Unified Modeling Language (UML) activity diagrams to visualize the generated tests. For more information on the Cadence Perspec System Verifier, please visit www.cadence.com/go/perspecpss10.
The Perspec System Verifier tests are optimized for each tool in the Cadence Verification Suite, including Cadence Xcelium Parallel Logic Simulation, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform. Additionally, the Perspec System Verifier integrates with the Cadence vManager Metric-Driven Signoff Platform to support the new use-case coverage in the PSS. Finally, the Perspec System Verifier generates tests that can utilize Cadence Verification IP (VIP), enabling re-use of the verification content via the PSS methodology, to achieve faster, more thorough SoC verification that requires less effort.

 

“Cadence’s support for the Accellera Portable Test and Stimulus Specification is critical for driving automotive IC innovation in our business,” said Thorsten Klose, lead principal engineer, Functional Verification at Infineon. “We’ve had proven success creating SoC tests with the Cadence Perspec System Verifier and managing verification closure with the vManager Metric-Driven Signoff Platform, enabling us to improve overall verification productivity by up to three months. With Cadence’s support for the new standard, we can execute with confidence and enable industry collaboration for verification of our new automotive application design projects.”

 

“The electronics industry has previously faced many challenges with verifying SoCs more effectively, and our collaboration with the Accellera Systems Initiative is the start of a new phase in the electronics industry that addresses these challenges,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence. “By providing support for the Portable Test and Stimulus Specification 1.0, the Perspec System Verifier and the broader Cadence Verification Suite deliver a production-proven SoC test generation toolset to improve design quality and accelerate verification.”

 

The Perspec System Verifier is part of the Cadence Verification Suite. Together, they support the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments. To learn more about the full Cadence Verification Suite, please visit www.cadence.com/go/verificationsuite.
About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine’s 100 Best Companies to Work For. Learn more at cadence.com.

Leave a Reply

featured blogs
Jul 16, 2018
This week it is CDNLive Japan on Friday July 20th. I will be there so obviously this will be my latest trip to Japan...but we will start by looking at my first trip to Japan. The first trip I made to Japan was in 1983. This was very early. If you have been in semiconductors o...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...
Jun 29, 2018
Once you'€™ve made the correct decision to add Speedcore eFPGA IP to your ASIC or SoC design, the next question you'€™ll need to answer is how large to make the eFPGA. That'€™s a multi-dimensional question because Speedcore eFPGAs contain many types of blocks including:...