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Cadence Announces Digital and Signoff Flow Support for Body-Bias Interpolation for GLOBALFOUNDRIES 22FDX™ Process Technology

Highlights:

•       Cadence tools enable customers creating designs across vertical markets to achieve optimized power and performance on GLOBALFOUNDRIES FD-SOI process nodes
•       Cadence and GLOBALFOUNDRIES collaborate on the delivery of a 22FDX™ reference flow and PDK

SAN JOSE, Calif., October 12, 2017 — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for the GLOBALFOUNDRIES 22FDX™ process technology. The Cadence® tools enable advanced-node customers across a variety of vertical markets — including automotive, mobile, internet of things (IoT) and consumer applications — to use GF’s fully depleted silicon-on-insulator (FD-SOI) architecture to optimize the power, performance and area (PPA).

For more information on the Cadence digital and signoff flow for GF’s FDX process, please visit www.cadence.com/go/dandsgf22fdx.

To facilitate the adoption of GF’s 22FDX process technology, Cadence has enabled body-bias interpolation calculations in the following  physical implementation and timing analysis tools:

•       Innovus™ Implementation System: An advanced physical implementation tool, incorporating a massively parallel architecture that helps designers deliver high-quality SoCs in less time with best-in-class PPA
•       Tempus™ Timing Signoff Solution: A complete timing analysis tool that improves signoff timing closure via massively parallel processing and physically aware timing optimization
In addition, Cadence and GF are actively working to enable the following solutions to support body bias interpolation on the 22FDX process:
•       Genus™ Synthesis Solution: An RTL synthesis and physical synthesis engine that improves productivity challenges faced by RTL designers, delivering up to 5X faster synthesis turnaround times
•       Voltus™ IC Power Integrity Solution: A cell-level power integrity solution supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip SoC power signoff accuracy

Cadence and GF also collaborated on the delivery of a GF 22FDX digital reference flow and a downloadable process design kit (PDK) that incorporates the Cadence digital and signoff tools.
“Our collaboration with Cadence helps validate its digital and signoff flows that support FDX body-bias interpolation, which is a key differentiator with our FD-SOI process technologies,” said Jai Durgam, vice president, Customer Design Enablement at GF. “This enablement within the Cadence tool suite allows our mutual customers to quickly and easily realize the performance, area and power benefits of 22FDX using body bias-interpolation techniques.”

“Through our support for body-bias interpolation, customers can confidently modify body-bias beyond the common usage of GF’s22FDX node to achieve optimal power and performance gains,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence. “Our efficient working model with GF helps customers implement designs quickly so they can remain competitive in their respective markets.”

About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine’s 100 Best Companies to Work For. Learn more at cadence.com.

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