industry news
Subscribe Now

Accellera Forms IP Security Assurance Working Group

Proposed standard will focus on known security concerns

Elk Grove, Calif., September 6, 2018 — Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of the IP Security Assurance Working Group.  The charter of the new working group is to provide a security assurance standard for hardware IP and its associated components to address security risks when integrated into embedded systems.

The formation of the IP Security Assurance Working Group (IPSA WG), in accordance with Accellera procedures, follows Proposed Working Group (PWG) activity that has been open to industry input since April 2018. The PWG had 45 participants from 20 companies including Silicon providers, IP vendors and EDA and verification vendors.  It has been meeting every two weeks since its inception to collect requirements, identify technical feasibility and industry interest and ultimately decide if it should move forward to develop the standard.

“As an industry organization, we are continually in search of and open to new opportunities to develop standards that improve design and verification productivity,” stated Lu Dai, Chair of Accellera. “The PWG demonstrated the clear need for a standard in this area, and the commitment from leaders in the industry was evident from the initial meeting.”

“The scope of this new working group is to focus on existing standards that pertain to IP specification, design, verification and integration where security risk is a concern,” stated Brent Sherman, IPSA WG Chair.  “There is no standard available to address security assurance in the development and delivery of IP, and the stakeholders involved are committed to working toward a standard that is comprehensive, flexible and scalable. I look forward to working with the Accellera members to develop and deliver this new standard to the community.”

The new working group will be meeting every 2 weeks, with the first meeting on October 2, 2018.  To find out more about the IPSA WG visit here.  If you are not already an Accellera member and are interested in joining to participate in the working group, visit here 

Background on IP Security Assurance Working Group

There is a certain level of risk when integrating third-party IP (3PIP) into silicon. The risk stems from unknown behaviors that may occur once integrated, which could result as an exploitable vulnerability.  Even if the source was provided, these unknowns may still exist since integrators typically treat 3PIP as “black-box” technology.  Silicon owners need a security assurance standard for acceptance before integrating 3PIP in order to minimize risk in their products.  High-quality silicon products are only such when they are built from high-quality IPs.

About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit Find out more about membership.Follow @accellera on Twitter or to comment, please use #accellera. Accellera Global Sponsors are: Cadence Design Systems, Inc.; Mentor, A Siemens Business; and Synopsys, Inc.

Leave a Reply

featured blogs
Sep 21, 2018
在这我们谈论的不是您的叠层设计跟其他人比怎么样,而是您设计的 PCB 层叠结构,是刚性板、柔性板、刚...
Sep 21, 2018
  FPGA luminary David Laws has just published a well-researched blog on the Computer History Museum'€™s Web site titled '€œWho invented the Microprocessor?'€ If you'€™re wildly waving your raised hand right now, going '€œOoo, Ooo, Ooo, Call on me!'€ to get ...
Sep 20, 2018
Last week, NVIDIA announced the release of the Jetson Xavier developer kit. The Jetson Xavier, which was developed in OrCAD, is designed to help developers prototype with robots, drones, and other......
Sep 18, 2018
Samtec performs several tests in-house as part of our qualification testing on a product series; including Low Level Contact Resistance (LLCR). It measures the amount of resistance in a position on a part. LLCR is used in combination with several other tests to track the over...