industry news
Subscribe to EE Journal Daily Newsletter

Pentek Introduces Jade Architecture Module for Extremely Wideband Signal Applications

 

  • 1-channel, 3.6 GHz or 2-channel, 1.8 GHz 12-bit A/D converter
  • Digital down converter (DDC) IP with up to 32x decimation
  • Jade architecture with Xilinx Kintex Ultrascale FPGA offers price, power and processing performance
  • advantages
  • Navigator Design Suite compatible with Xilinx’s Plug-and-Play Vivado IP Integrator expedites development 

UPPER SADDLE RIVER, NJ? Pentek, Inc., today introduced the newest member of the Jade™ family of high-performance data converter XMC FPGA modules: the Jade Model 71841, a 1-channel, 3.6 GHz 12-bit A/D or 2-channel, 1.8 GHz 12-bit A/D XMC module based on the Xilinx Kintex Ultrascale FPGA.

Performance IP Cores

The Model 71841 comes preconfigured with a suite of built-in functions for data capture, synchronization, time tagging and formatting, making it an ideal turn-key interface for radar, communications or general data acquisition applications. The Model 71841 features an A/D acquisition IP module and a programmable DDC for easy data capture and moving. Single-channel mode decimation can be programmed to 8, 16 and all values from 32 to 528 in steps of 16. Dual-channel mode decimation can be programmed to 4, 8 and all values from 16 to 256 in steps of 8 with both channels sharing the same decimation rate. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC to the A/D sampling frequency.

“The Model 71841 significantly boosts the performance, with considerable savings in power, cost, and even weight,” said Bob Sgandurra, director of Product Development of Pentek. “Our customers are excited to take advantage of the Jade Architecture and our Navigator design suite in their next development cycle.”

A/D Converter Stage

The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. A programmable 15-bit gain adjustment allows the Model 71841 to have a full-scale input range of +2 dBm to +4 dBm. A built-in Auto Sync feature supports A/D synchronization across multiple modules.

Breakthrough Performance with the Jade Architecture

Evolved from proven designs of the Pentek Cobalt® and Onyx® architectures, the Jade architecture is based on the Xilinx Kintex UltraScale FPGA, which raises the digital signal processing (DSP) performance by over 50%. Equally impressive are reductions in cost, power dissipation, and weight.

As the central feature of the Jade architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. Jade supports an optional 5 GB bank of DDR4 SDRAM memory for custom applications. The memory to Gen.3 x8 PCIe link can sustain 6.4 GB/s data transfers, a 20% improvement over the Onyx architecture. Eight additional gigabit serial lanes and LVDS general purpose I/O lines are available for custom solutions.

Navigator Design Suite Efficiencies Streamline IP Development

Pentek’s Navigator™ Design Suite was designed from the ground up to work with Pentek’s Jade architecture and Xilinx’s Vivado Design Suite® providing an unparalleled plug-and-play solution to the complex task of IP and control software creation and compatibility. The Navigator Design Suite consists of two components: Navigator FDK (FPGA Design Kit) for integrating custom IP into Pentek sourced designs and Navigator BSP (Board Support Package) for creating host applications. Users can work efficiently at the API level for software development and with an intuitive graphical interface for IP design.

Pentek’s Navigator FDK provides complete data acquisition and processing IP. When the design is opened in Vivado’s IP Integrator, the developer can access every component of the Pentek design, replacing or modifying blocks as needed for a specific application. All blocks use industry standard AXI4 interfaces providing a well-defined format for custom IP to connect to the rest of the design. In addition to the IP specific to the supported Jade board, Navigator also includes processing blocks for some of the most commonly used algorithms.

Navigator BSP enables complete operational control of the hardware and all IP functions in the FPGA. It provides a well-defined API, allowing developers to create their applications at a high level of abstraction. Built on C-language libraries, it contains a complete suite of initialization, control and status functions, as well as a rich set of precompiled, ready-to-run-examples. Navigator BSP also includes the Signal Analyzer, a full-featured analysis tool that displays data in time and frequency domains. The Pentek Navigator BSP is available for Windows and Linux operating systems.

For systems that require custom functions, IP can be developed using the Pentek GateFlow® FPGA Design Kit, extending or even replacing the factory-installed functions.

Pre-Configured SPARK System Ready for Immediate Use 

With a Pentek 8266 SPARK® PC, 8264 SPARK 6U VPX, or 8267 SPARK 3U VPX development system, work can begin immediately on applications. A SPARK system saves engineers time and expense associated with building and testing a development system and ensures optimum performance of Pentek boards. SPARK development systems are ready for immediate operation with software and hardware installed. In many applications, the SPARK development system can become the final deployed application platform.

Form Factors

The Model 71841 XMC module is designed to operate with the wide range of carrier boards in PCIe, 3U & 6U VPX, AMC, and 3U & 6U CompactPCI form factors, with versions for both commercial and rugged environments.

Pricing and Availability

Designed for air-cooled, conduction-cooled, and rugged operating environments, the Model 71841 XMC module with 5 GB of DDR4 SDRAM starts at $16,195 USD. Additional FPGA options are available. Delivery is 8 to 10 weeks ARO. For the latest pricing and availability information, please contact Mario Schiavone by phone at (201) 818-5900 ext.229, or by email at mario@pentek.com.

About Pentek

Pentek, an ISO 9001:2008 certified company, designs, manufactures and markets innovative COTS and rugged DSP boards and system recorders for commercial, government and military systems, including radar, communications, medical and industrial control applications. Pentek offers powerful VME, VPX, VXS, FMC, XMC, cPCI, PCIe and AMC boards for data acquisition, software radio and digital signal processing featuring Xilinx FPGAs. Pentek’s high-speed real-time recording systems are pre-configured and can be used in the lab or deployed in the field. Pentek equips all boards and recorder products with high-performance I/O including gigabit serial interfaces, powerful software development tools and offers strong DSP software support.

Leave a Reply

featured blogs
Oct 18, 2017
Rob Aitken is digging a bit deeper into what it would really take to connect a trillion things in his keynote next Thursday at Arm TechCon How to Build and Connect a Trillion Things . What would those things be? What might unit volumes be? How could we power them? Secure them...
Oct 18, 2017
As consumers, no one ever complains that their wireless connectivity is “too fast”. Global wireless carriers and network providers continue to push the limits of 4G LTE, but a next-generation wireless standard – 5G New Radio (5G NR) – is on the horizo...
Sep 12, 2017
Torrents of packets will cascade into the data center: endless streams of data from the Internet of Things (IoT), massive flows of cellular network traffic into virtualized network functions, bursts of input to Web applications. And hidden in the cascades, far darker bits try...
Sep 29, 2017
Our existing customers ask us some pretty big questions: “How can this technology implement a step-change in my specific process? How can Speedcore IP be integrated in my SoC? How can you increase the performance of my ASIC?” We revel in answering such questions. Ho...