Belgrade, Serbia, October 13th, 2010 – HDL Design House has announced today the availability of the HIPA 21000, a high performance low cost serializer-deserializer (SerDes) meant to be used in the systems based on Serial RapidIO protocol. It can also be used with any protocol that supports 8b/10b encoding and similar baud rates as Rapid IO serial protocol. Serial data transfer rate is to be chosen between five different values: 1.25Gbaud/s, 2.5Gbaud/s, 3.125Gbaud/s, 5Gbaud/s, 6.25Gbaud/s.
The IP core can be used with the digital SRIO 2.1 IP core (HIP 3300) developed by HDL Design House.
The main features of the HIPA 21000 SerDes are:
- Single power supply voltage. It reduces cost for two power supply sources.
- Extracted clock from received data is available. It enables users to adjust clock for the digital part to be in phase with incoming data.
- Rapid IO protocol (version 2.1) is supported. Data transfer rates from 1.25Gbaud/s to 6.25 Gbaud/s are supported and communication is bidirectional. This IP core can be used as a module in both master and slave in communication.
- Adaptable data transfer rate.
- Parallel data 20 bit wide which implies frequency of parallel clock is twenty times lower than serial clock, which is maximal 312.5MHz.
- Minimal number of external components. The only external components needed are blocking capacitors for filtering power supply noise and reference voltage source for proper operation.
- Programmable Tx pre-emphasis and Rx post-equalization. To avoid low BER (bit error rate) after the degeneration of signal in communication, channel equalizers are built in. There are equalizers for both receiver and transmitter and they are programmable independently.
- Referent clock is needed. The frequency of such clock should be roughly 20 times lower than data transfer rate of interest.
- Power down mode is available. There is a power down signal active high which drives the SerDes in power down mode. This mode enables power saving when there are no data transfer.
HDL Design House provides IP cores for reuse along with IP core customization services to meet specific customer needs. This customization service includes migration to another technology vendor. Optimized for today’s SoC designs, these IP cores are supported with full documentation, including architectural specifications and detailed test specification. Full integration support is available.
If you are interested in finding out more about the HIPA 21000 IP core, please visit www.hdl-dh.com or download the datasheet from the following link:
http://www.hdl-dh.com/prodbroch/HIPA21000.17.07.2010.pdf
About HDL Design House:
HDL Design House delivers leading-edge digital and analog, design and verification services and products in numerous areas of SoC and complex FPGA designs. The company develops IP cores and provides complete design and verification services for complex SoC projects. The company also delivers component (VITAL) models for major SoC product developers. Dedicated to fulfilling each customer’s unique requirement, HDL Design House has established a reputation as a reliable partner with high-quality products and services, flexible licensing models, competitive pricing and responsible technical support. The company enables customers to concentrate on system-level work and be confident that the various system components have been fully and reliably engineered and tested.
Founded in 2001, HDL Design House has 60 employees in two design centers – in Belgrade and Cuprija (Serbia). The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS), thereby meeting United Kingdom Accreditation Service (UKAS) regulatory requirements. With ISO 27001:2005 certification, the highest certification standard for information security available, HDL Design House becomes the first company in Serbia to comply with this standard. In 2006 the company was awarded the SME Exporter of the Year by Serbia Investment and Export Promotion Agency (SIEPA).
