Belgrade, Serbia – November 3rd, 2009 – HDL Design House has announced I2S soft IP core(HIP 3700). HIP 3700 I2S soft IP core is based on a generic, highly modular architecture from which a variety of solutions can be easily created to effectively and efficiently address customers’ specific requirements. I2S is an audio transmission standard, used to connect system elements such as Analog to Digital and Digital to Analog converters, speakers or audio subsystems. HIP 3700 is silicon proven I2S Controller IP Core compliant with the Philips* Inter-IC Sound specification. IP Core provides up to 8 audio channels and a 32-bit parallel processor bus as the application interface. Each channel can be programmed as an I2S master or an I2S slave.
HIP3700 IP Core Key Features:
IP core meets the Philips Inter-IC Sound bus specification
Supports configurable 8/16/24/32 bit DAC/ADC resolution
Supports Master/Slave and Receiver/Transmitter modes
Two sets of SCK (SCLK) and WS strobes:
– One for all transmitters
– One for all receivers
32-bit parallel AMBA APB processor bus (other custom specific buses can also be provided upon request)
– Configurable internal FIFO’s (one for all transmitter channels and one for all receiver channels)
– Audio sampling capabilities:8, 16, 24, 32, 44.1,48; 88.2; 96; 176.4; 192kHz
– The I2S Bus Interface may operate in one of the following four configurations:
– I2S – Philips mode
– Left Justified mode
– Right Justified mode
– DSP mode
– Mode of operation for each channel can be set in the single configuration register IRQ driven by the I2S bus events
The I2S IP core can be utilized for a variety of Inter-IC Sound compliant serial bus applications:
ASIC and SoC applications requiring up to 8 channel audio data transmission
Digital signal processing and multimedia systems
Connecting Analog to Digital and Digital to Analog converters
Digital audio interface of embedded microcontroller systems
HDL DH provides, as part of the IP licensing package, an extensive set of documentation and customer support capabilities. The IP package consists of Verilog RTL code and detailed design documentations. HDL DH also offers a suite of design services for customization and integration of the IP cores into each customer’s ICs and FPGAs. HDL DH also provides a variety of verification solutions including I2S protocols. The I2S verification solution may be part of HIP 3700 soft IP core delivery, depending on customer requirements.
If you are interested in finding out more about the HIP 3700 IP core, please visit www.hdl-dh.com or download the datasheet from the following link: http://www.hdl-dh.com/ipproducts.html
About HDL Design House:
HDL Design House delivers leading-edge design and verification services and products in numerous areas of SoC and complex FPGA designs. The company develops IP cores and provides complete design and verification services for complex SoC projects. The company also delivers component (VITAL) models for major SoC product developers. Dedicated to fulfilling each customer’s unique requirements, HDL Design House has established a reputation as a reliable partner with high-quality products and services, flexible licensing models, competitive pricing and responsible technical support. The company enables customers to concentrate on system-level work and be confident that the various system components have been fully and reliably engineered and tested.
Founded in 2001, HDL Design House has 62 employees in two design centers – in Belgrade and Cuprija (Serbia). The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS), thereby meeting United Kingdom Accreditation Service (UKAS) regulatory requirements. With ISO 27001:2005 certification, the highest certification standard for information security available, HDL Design House becomes the first company in Serbia to comply with this standard. In 2006 the company was awarded the SME Exporter of the Year by Serbia Investment and Export Promotion Agency (SIEPA).
