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Stop Repeating Yourself

by Bryon Moyer

May 20, 2011 at 12:52 PM

You may recall a while back – actually, a good while back – we looked at parasitic extraction tools and contrasted the field solver approach with Silicon Frontline’s random-walk approach. Reprised really briefly, with the random walk approach, rather than dividing the entire structure up into chunks and solving the whole thing, you follow lots of random paths through dielectric until you hit metal, and, statistically, you end up with the precision needed to determine the parasitics in all three dimensions.

As with all such compute-intensive jobs, the goal is to do it faster than the other guy. Hierarchy turns out to be very useful for that. And Silicon Frontline has just released a new extraction tool, H3D, that leverages hierarchy to achieve “sub-linear” performance: that is, time to completion slows down less than linearly with growth in circuit size.

The idea of using hierarchy is that, if you have a particular cell that you use lots of times, don’t re-solve it every time. If you can recognize that you’ve been there before, then you can move on.

That may sound trivial, but it’s not so simple. As much as possible, H3D uses any hierarchy present in the input file, which sounds pretty obvious. But here’s the deal: it can add hierarchy and it can drop it.

Let’s say that there’s a circuit that’s re-used several times in the design with exactly the same layout and that it’s defined as a block in the input file. The simplistic answer would be to solve it once and pass the answer around to the others. But you can’t quite do that. If one of them is laid out next to a quiet analog block and the other next to some high-drive I/Os, well, they’re no longer the same due to coupling with their neighbors.

So H3D will do some sample walks to determine whether the two instances should, in fact, be treated the same. They claim to have a mathematically rigorous way of deciding when to keep or drop the hierarchy.

By a similar method, they can sometimes identify hierarchy where none was specified in the input. In fact, they can even occasionally do that by a simpler geometric test, but usually they have to do some walks to be sure. You can imagine that if they wanted to be able to find all hierarchy in the design, that becomes a rather laborious pattern-matching problem (you would more or less have to save everything you ever solve and then search that space each time you checked out something new… even with clever techniques, that just sounds like a lot of work). Presumably that’s at least one reason why they don’t claim to take a flat file and automatically discover any inherent hierarchy for you.

Note that this doesn’t just save time in the extraction process; it also saves time in the simulations that the extraction drives.

More details in their release

Channels

EDA. Semiconductor.

 
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