Back in 2000 (or thereabouts) I sat in the audience in an auditorium at Altera for a big announcement. In attendance were both Pomp and Circumstance. FPGAs were graduating to the big leagues. No longer content to be the glue-logic parts cobbled on at the end of the design to make the whosit chip talk to the whatsit driver, FPGAs were taking over the System.
Altera had coined a new term: “System-on-Programmable-Chip” (SoPC). SoPC was the future, and Altera was delivering on that future vision RIGHT NOW. The company was rolling out a new software suite, a new generation of devices, and an FPGA family with embedded ARM and MIPS microprocessors. Jetpacks, personal robots, and video-phones could move aside – the real future was FPGAs containing embedded computing systems.
Altera was right.
Altera’s first SoPC line failed dismally.
However, just as the famously-failed Apple Newton may be the ancient ancestor of the current mega-successful iPhone and iPad, Altera’s less-than-Arthurian Excalibur FPGA line set the stage for a flurry of FPGA-based embedded computing technology that has occupied much of the industry for the intervening decade. On the heels of the Excalibur disaster, Altera came back with a vengeance, launching the Nios soft-core embedded processor architecture that took the market by storm.
In the battle for embedded-system-on-FPGA supremacy that has ensued, Xilinx has offered PowerPCs in hard-core form, MicroBlaze and picoBlaze soft-cores, and a number of other fringe solutions. Altera has built an embedded empire around their Nios and Nios II success with the addition of third-party soft cores for specialized applications. Actel partnered with ARM to deliver devices that combine programmable flash-based FPGA fabric with industry-standard microcontrollers. Everybody has some form of 8051 available. All three companies delivered tools, tools, and more tools.
FPGA companies wooed embedded developers – bidding them to mend their monolithic ways and jump on the embedded FPGA bandwagon. Worried about FPGA processor performance? Just accelerate the critical parts of your algorithm in hardware – right on the chip. There – all fixed. Like your Eclipse-based software development tools? No problem, we’ve got some too – oops, hang on… OK, there. Now we have Eclipse-based tools too.
In those early days, embedded developers dropped their traditional embedded computing architectures and embraced FPGA-based embedded computing in droves. Wait, make that just “drove.” Something like 0.000002% of embedded designers started using FPGAs – and that turns out to be a big deal in the FPGA market. Because, while there are maybe a couple hundred thousand FPGA designers worldwide, there are an estimated Avogadro’s Number of embedded designers. If you took Chemistry, you know that even 0.000002% of Avogadro’s Number is still really a lot. If you don’t think so, please send me that many dollars.
This week, Altera called me for an announcement that was reminiscent of that year-2000 millennial milestone meeting – but without the big auditorium, the sound system, the snazzy-swag giveaways, the lighting effects, and the pretentious PowerPoint slides. Actually, it was more like a conference call that I took on the sofa with my iPhone. The message, however, was major league. Altera is making a significant acceleration in their embedded strategy. They are broadening their array of FPGA-plus-processor options and completely re-vamping their tool suite for embedded designers.
The venerable Nios II processor core will be joined by a new, and reportedly highly-capable, MIPS32 architecture soft-core dubbed MP32, and a future device family that will contain hard-core ARM-9 processing subsystems. About a year ago, we did a piece about Altera announcing a partnership with MIPS to develop something new and Xilinx announcing a partnership with ARM. We speculated about what it all might mean (click here). Our batting average was pretty good – as we can now seen a lot more of the details through the fog.
Now that we see that Altera is playing ball with both MIPS and ARM (again) the speculation that Xilinx and Altera would take opposite sides in an ARM/MIPS positioning is off the table. Altera will cover both camps, and they will have offerings that cater to embedded system designers coming from either background and, more importantly, with either kind of legacy software.
Why is the MP32 a soft core and the ARM-9 a hard core? Well, we’re back to speculation again. By putting an ARM-9 on an FPGA (versus, say, a more “microcontroller” architecture like a Cortex-M3), Altera is clearly going after the higher-performance segment. For those folks, a hardened core will run faster, with less power, consuming less silicon area. All wins.
In the case of the MIPS core, we know less. When Altera announced the partnership about a year ago, they said it was in response to key customers that had a need for MIPS architecture in their FPGA-based embedded designs. We don’t know who those customers are, or what they wanted with the MIPS architecture. In general, we assume that a “standard” architecture (like MIPS or ARM) ported to FPGA soft-core will be nowhere near the efficiency of a purpose-built-for-FPGA soft-core like Altera Nios II or Xilinx MicroBlaze. Altera assures us that this is not the case for M32, however. The company claims that M32 will have a very competitive performance profile when compared with other soft-core processors. A soft-core implementation means considerably more flexibility than a hard core – particularly for things like creating multi-core (or even massively multi-core) architectures. Perhaps the people that wanted MIPS architecture would rather have a lot of them instead of a smaller number of faster hard-cores. This particularly makes sense in light of the MIPS strategy that Jim Turley documents in this week’s Embedded Technology Journal (click here).
In addition to the new cores, Altera is announcing a brand-spanking new tool set to complement their enhanced embedded offering. For the past ten years or so – SoPC Builder has been the company’s answer to “how do I build an embedded system on an FPGA?” SoPC Builder is a simple, intuitive tool that allows even a non-expert to quickly stitch together an embedded system – complete with processor, busses, and peripherals. Today, however, the technical demands have gone up a level or two. Network-on-a-chip is in, and busses are passe. Multi-core is a reality. Memory mapping and memory management are part of many system architectures. Overall, the problem of building an embedded system has gotten more complicated, and the tools have to grow with it. Altera is announcing their new Qsys embedded development tool – which the company says will satisfy the modern-era requirements, including hierarchical design, more advanced interconnects, and more advanced architectures. Qsys will be available later this year.
As a sidenote to this process – Altera is also part of Intel’s “Stellarton” project, which is not yet fully announced, but which will contain an Atom processor sharing a package with an Altera FPGA. While we don’t know much about this project yet, the possibilities are intriguing. Obviously a major socket win for Altera, it also promises an embedded architecture that’s the flip-side of embedded cores on FPGAs, but with some similar properties. Imagine putting peripherals and accelerators in the FPGA fabric while the Atom processor handles most of the software duty. By having this as a fixed part of the product, reference designs and software can count on the FPGA component being there and being connected in a known structure. It should be fun to watch as it evolves.
In the competitive space, it’s clear that Altera and Xilinx continue to struggle for long-term supremacy in the embedded-FPGA space. Amidst the dueling announcements of future products we find some truly exciting product possibilities. You’d better warm up your coding fingers.
