fish fry
Subscribe Now

Bridge Over Pixelated Water

CrossLink Changes the Camera Interface Game

We’re talking about the building blocks of electronic design in this week’s Fish Fry. First, we take a closer look at some groundbreaking transistor technology. We investigate new research coming out of the Moscow Institute of Physics and Technology that could finally make graphene tunneling transistors a reality. Also this week, we examine Lattice Semiconductor’s CrossLink pASSP with Subra Chandramouli. Subra and I dive down into the details of this new programmable bridging device and reveal how ASSP and the FPGA parts of the CrossLink story can help you with your next camera or interface-enhanced design. 

 

 

Download this episode (right click and save)

Links for May 27, 2016

More information about Lattice Semiconductor

More information about CrossLink™

Feature Article by Jim Turley: The World’s Best Multiplexer – Lattice CrossLink pASSP Fits Into the Odd Spaces in New Designs

Abrupt current switching in graphene bilayer tunnel transistors enabled by van Hove singularities (Whitepaper)

Leave a Reply

featured blogs
Aug 20, 2018
Xilinx is holding three Developer Forums later this year and registration for the two October events is now open. The US event is being held at the Fairmont Hotel in downtown San Jose on October 1-2. The Beijing event is being held at the Beijing International Hotel on Octobe...
Aug 20, 2018
'€œCircle the wagons.'€ We can find wisdom in these Pilgrim words. The majority of multi-layer printed circuit boards feature at least one, and often a few or several layers that are a ground pour. The b...
Aug 20, 2018
Last summer, I took Fridays to write about technology museums. I planned to do a series on Fridays this summer on the odd jobs that I have done in my life before I started what you might consider my real career. But then Cadence Cloud took precedence. But now it is the dog-da...
Aug 17, 2018
Samtec’s growing portfolio of high-performance Silicon-to-Silicon'„¢ Applications Solutions answer the design challenges of routing 56 Gbps signals through a system. However, finding the ideal solution in a single-click probably is an obstacle. Samtec last updated the...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...