fish fry
Subscribe Now

Treasure of the Semiconductor Madre

Seeking EDA Gold (and Answers) with Xerxes Wania

Bust out the pickaxes and dynamite, we’re looking for gold in ‘dem ‘der hills. Xerxes Wania (CEO – Sidense) joins Fish Fry this week to dig into the treasure trove of issues found deep in the semiconductor and EDA industries today. Xerxes and I scour the land for faults and break out our trusty gold pans to find the answers… and it ain’t pretty my friends. Also this week, I delve into a brand new world of inductance-to-digital converters that will revolutionize position and rotation sensing in our IoT designs.


 

Download this episode (right click and save)

Links for June 26, 2015

More information about Sidense

New Episode of Chalk Talk:  Inductance-to-Digital Converters Revolutionize Position & Rotation Sensing


Leave a Reply

featured blogs
Aug 17, 2018
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the compa...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...