fish fry
Subscribe Now

V for Verification

DVCon 2012 Breakdown

Welcome to the soothing waters of verification. Jump right in, the water is warm! This week’s Fish Fry is all about design verification and DVCon 2012. I sift through all of the details of this year’s show: the keynote, the various announcements unveiled at the show, the happy hour expo show hours and even the eerie decor of the Doubletree Hotel.  In a special DVCon interview double header I chat with both Shakeel Jeeawoody (Blue Pearl Software) about getting your constraints right for HDL-based designs, and I also chat with Anupam Bakshi (CEO – Agnisys) about how Agnisys is attacking a brand new part of the EDA/verification market. 

I also have yet another ultra fantastic MAX V CPLD Development kit (courtesy of Altera) to give away this week, but you’ll have to tune in to find out how to win.

 

Watch Previous Fish Frys

Fish Fry Links – March 2, 2012

More information about DVCon 2012

More information about Blue Pearl Software

Blue Pearl Announces Release 6.0 of EDA Software Suite

More information about Agnisys

Agnisys offers free Register Generator for UVM

More information about Altera’s MAX V CPLD Development Kit

Fish Fry Executive Interviews

Moshe Gavrielov, CEO – Xilinx

John Bruggeman, Former CMO – Cadence Design Systems

Darrin Billerbeck, CEO – Lattice Semiconductor

Lauro Rizzatti, Vice President of Marketing, EVE

Bill Neifert, CTO – Carbon Design Systems

Sean Dart, CEO – Forte Design Systems

Kapil Shankar, Former CEO – SiliconBlue

Andy Pease, CEO – QuickLogic

Rajeev Madhavan, Former CEO – Magma 

Paul Kocher, President – Cryptography Research Inc.


Leave a Reply

featured blogs
Oct 22, 2018
At the start of November last year, Cadence announced that it was acquiring nusemi, a company focused on the development of high-speed SerDes interfaces. Today, Cadence demonstrated working 7nm SerDes testchips running at 112 Gbps. It is hard to comprehend speeds like this. O...
Oct 19, 2018
Any engineer who has designed an IC-based solution likely used some sort of HW development tool. Semiconductor manufacturers have a long history of providing engineers with the HW tools needed to test their silicon. Evaluation platforms, like the Xilinx® Zynq UltraScale+ ...
Oct 16, 2018
  IC Insights has just published the September Update to The 2018 McClean Report, and one figure (reproduced below) puts yet another nail into the coffin for poor old Moore'€™s Law. Now please take care. There'€™s a vertical line between the 200mm wafers on the left ...
Oct 12, 2018
At the end of the day, your products are only as good as their in-the-field performance. It doesn'€™t matter how well they performed in a controlled environment....