In the forum thread about Altium’s move to China, I was asked to comment on the “negative” aspects of the EDA space in general, and how that relates to Altium’s situation. We certainly don’t want to come off as “Pollyanna Engineering Journal,” so here goes.
First, as to why we write so frequently about Altium – it is because they make a lot of aggressive strategy moves. Aggressive moves – whether they’re good or … Read More → "Par for the Course"
It’s tough not being a domain specialist at times. You get hit by scary-sounding jargon that you mostly hope you can evade without having to parse and understand it. And none sounds more imposing than the thing that came up in the wind sensor article, the delta-sigma modulator
That sounds like one of … Read More → "Analog Roosters Taking Digital Drinks"
Last week Cadence announced a new wide-I/O memory controller IP block, ostensibly the first of its kind. This actually represents a risk start based on a JEDEC standard that’s not yet complete.
Many of us grew up knowing that you can’t have truly random numbers in your algorithms or circuits. The best you can do is “pseudo-random,” which means take a non-random number and shake it up really hard so it looks random. But… if you start with the same number every time, then you’ll end up with the same sequence every time.
Oh yeah, that’s the other thing: pseudo-random number generators (PNRGs) are all about sequences. You seed the thing with a value, and, from then on, it supplies … Read More → "Dude, That’s So Random"
A couple years ago we looked at the possibility that non-volatile memory (NVM) might have a limited future. Given that the main physical mechanism of concern at the time was floating gate leakage through excessive tunneling, it certainly seems to give an edge to the one-time programmable (OTP) guys when it comes to migration to advanced nodes. They use anti-fuses instead of floating gates, and so aren’ … Read More → "28-nm NVM Lives"
It looks like the chip packaging industry may be getting a new competitor.
I spent a few minutes with TSMC’s Sr. VP for R&D Shang-yi Chiang last week at the TSMC Symposium to follow up on one of the topics he had raised in his presentation, that of low-K dielectrics and some of the impact they were having.
For those of us not as deeply steeped in this stuff, it’s easy to get confused by low-K and high-K, since they are both trumpeted as important new developments. High-K is … Read More → "TSMC Going for the Whole Package"