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Par for the Course

In the forum thread about Altium’s move to China, I was asked to comment on the “negative” aspects of the EDA space in general, and how that relates to Altium’s situation.  We certainly don’t want to come off as “Pollyanna Engineering Journal,” so here goes.

First, as to why we write so frequently about Altium – it is because they make a lot of aggressive strategy moves.  Aggressive moves – whether they’re good or … Read More → "Par for the Course"

Go Wide

Last week Cadence announced a new wide-I/O memory controller IP block, ostensibly the first of its kind. This actually represents a risk start based on a JEDEC standard that’s not yet complete.

The idea behind the wide-I/O movement is predicated on use in 3D ICs, where a memory chip will be stacked on a logic chip, with the connections being made by TSVsRead More → "Go Wide"

Dude, That’s So Random

Many of us grew up knowing that you can’t have truly random numbers in your algorithms or circuits. The best you can do is “pseudo-random,” which means take a non-random number and shake it up really hard so it looks random. But… if you start with the same number every time, then you’ll end up with the same sequence every time.

Oh yeah, that’s the other thing: pseudo-random number generators (PNRGs) are all about sequences. You seed the thing with a value, and, from then on, it supplies … Read More → "Dude, That’s So Random"

TSMC Going for the Whole Package

It looks like the chip packaging industry may be getting a new competitor.

I spent a few minutes with TSMC’s Sr. VP for R&D Shang-yi Chiang last week at the TSMC Symposium to follow up on one of the topics he had raised in his presentation, that of low-K dielectrics and some of the impact they were having.

For those of us not as deeply steeped in this stuff, it’s easy to get confused by low-K and high-K, since they are both trumpeted as important new developments. High-K is … Read More → "TSMC Going for the Whole Package"

featured blogs
Oct 22, 2018
At the start of November last year, Cadence announced that it was acquiring nusemi, a company focused on the development of high-speed SerDes interfaces. Today, Cadence demonstrated working 7nm SerDes testchips running at 112 Gbps. It is hard to comprehend speeds like this. O...
Oct 19, 2018
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Oct 16, 2018
  IC Insights has just published the September Update to The 2018 McClean Report, and one figure (reproduced below) puts yet another nail into the coffin for poor old Moore'€™s Law. Now please take care. There'€™s a vertical line between the 200mm wafers on the left ...
Oct 12, 2018
At the end of the day, your products are only as good as their in-the-field performance. It doesn'€™t matter how well they performed in a controlled environment....