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A Non-FinFET Path to 10 nm

Do you see FD-SOI as a useful partner to FinFET technology for non-performance-intensive designs?

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The Internet of Seeing Things

Kevin:

Intelligent Vision or "Embedded Vision" is the killer app that I had in mind when we started developing ZYNQ at Xilinx in 2008 ! In 2011, Jeff Bier and I started the Embedded Vision Alliance to help educate and teach developers how to add Intel…

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A 1T (or 2T) SRAM Bit Cell

In terms of functionality, you're correct that it can be thought of as 3T. However, with regards to the area footprint, it is 1T (the cell size at 28 nm is 0.025um2, compared with 6T size of 0.127um2). The schematic cell drawing in this article includes a…

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Who Owns the IoT Gateway?

What do you think the future configuration of the IoT gateway will be like?

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High-Level Design for Everyone

Highlevel Language Design Methodologies sounds great to me.
One question: Why only C and C++ as the highlevel languages?
Wouldn't there be interest in using languages like Java, Python, Scala, Clojure etc. for direct FPGA synthesis. If a couple highlev…

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EDA: Expanding or Fading?

Most of the current EDA tools and methodology are well past their prime. The high variability in sub 45nm Silicon means you want to move to asynchronous design techniques, and the move to die-stacking means you need aggressive power management - being abl…

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