In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.
PDN designs targeting transceiver (SERDES) FPGAs require clean voltage sources with strict voltage rail requirements. This document describes the advantages of modern switching voltage regulators in a power distribution network (PDN) design to achieve the best FPGA transceiver performance. This white paper provides guidance on voltage regulator selection for low-noise applications, and a test case that demonstrates the transceiver performance for different types of voltage regulators and voltage rail configurations.
How can a designer use commercially available IP within a DO-254 compliant system?
This white paper covers the challenges of backplane applications and how to use the features of Altera® Stratix® V GX and GS FPGAs to address the range of problems that are encountered in backplane applications such as 10GBASE-KR.
Learn how the timing constraints wizard can be used to “completely” constrain your design. The wizard adheres to the UltraFast™ design methodology defining your clocks, clock interactions, and finally your input and output constraints. In this video, you will see the wizard transform a partially constrained design into a fully constrained design that passes timing.
This white paper describes how Altera's jitter/noise eye (JNEye) link analysis tool enhances HSIO link modeling and simulation. This paper includes simulation and experimental results that demonstrate how the JNEye tool can meet the requirements for accuracy and advanced simulation and modeling techniques.
Having trouble meeting deadlines? Is your FPGA design growing but when you look around, your team is still the same size, or worse, smaller? Do you wish reusing someone else’s design would work seamlessly? Watch this webcast to see how you can increase your FPGA design productivity. Find out how to quickly develop large, complex systems by integrating other smaller complete systems and intellectual property (IP).
Transferring High-Speed Data over Long Distances with Combined FPGA and Multichannel Optical Modules
Today’s copper-based high-speed serial interfaces can deliver data at multi-gigabit rates. Data transfer rates exceeding 100 Gbps are possible by using multiple lanes in parallel, but are limited in the distance they can travel. One approach that improves the distance is to use optical interconnects rather than copper. Altera Corporation and Avago Technologies Inc. have jointly developed a solution that combines an FPGA and optical transmitter and receiver modules into a single integrated solution that can replace copper interconnects and multiple card-edge optical transceivers.
SmartFusion2 FPGAs: Breakthrough Capabilities for Advanced Security, High Reliability and Low Power FPGA Applications
Microsemi has created the new SmartFusion®2 family of system-on-chip (SoC) field programmable gate arrays (FPGAs), which directly address these challenges and deliver the advanced security, high reliability and low power capabilities that this growing class of mission critical applications demands. Additionally, Microsemi believes that these requirements are no longer relegated to a narrow class of applications, but span a majority of the deeply interconnected electronics systems being designed today. This white paper will illustrate how the Microsemi SmartFusion2 family holds the promise of creating a much more secure and reliable future for all of us.
Metastability is a phenomenon that can cause system failure in digital devices when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This paper describes metastability in FPGAs, explains why the phenomenon occurs, and discusses how it causes design failures. The MTBF due to metastability indicates whether steps should be taken to reduce the chance of such failures. This paper explains how MTBF is calculated, and how both vendors and designers can increase it.
The availability of devices incorporating hardened ARM® applications processors closely coupled to an on-chip FPGA fabric opens a world of possibilities to electronic system designers. However, these devices also introduce novel design, debug, and optimization challenges. New development methodologies are required to address software and hardware integration issues and system-level performance optimizations efficiently at a price affordable by small- and medium-sized companies. This white paper outlines Altera and ARM’s latest innovations in on-chip debug logic, FPGAs, and software debug and analysis tools aimed to address these challenges.
In this webcast, we'll take a look at some of the typical system and consumer application requirements, and see how MachXO2 devices address these requirements. We'll also talk about the MachXO2 PLD feature set and discuss some of the available tools that enable you to evaluate and start designing with MachXO2 devices.
This white paper looks at Industrial Ethernet implementation options from the point of view of the factory automation vendor developing slave systems, such as I/O modules and drives.
Over 70% of designs on Altera® FPGAs require some type of external memory in the design, but the needs vary depending on the individual application. This white paper addresses all aspects of building external memory solutions with Altera FPGAs, including application needs, memory capabilities of Altera FPGAs, and device and IP selection. Also discussed is the modular style of the memory components, comprised of Altera’s controller and PHY offerings with circuit and calibration features.
If you are seeking a device that is fast, reliable, and gives you high bandwidth, seek no further. Our 28-nm Stratix® V FPGAs are just what you need for your high-end designs such as 100G applications. Watch this 5-minute video to get an initial look at our high-performance Stratix V FPGA running at 28 Gbps. You will: See the transmit eye at 28 Gbps running a PRBS-31 test pattern, See the receiver performance at 28 Gbps, and learn about the transceiver architecture that provides high performance, power efficiency, and reliability.