With our Transceiver Signal Integrity Development Kit, Stratix V GX Edition and the Transceiver Toolkit tool in Quartus II software, you can easily and efficiently evaluate the performance of the high-speed serial transceivers in the Stratix V FPGA.
IGLOO®2 devices have a range of differentiated security features, including a secure boot feature, which verifies that the boot code used to ‘bring-up’ an embedded system is authorized to run on the target processor. Without this check of the MCU, a malicious intruder can compromise the entire system. This paper outlines the dangers of poor system security and illustrates how implementing a secure boot can dramatically increase the security of embedded systems. It also shows how secure boot may be included for free, since IGLOO2 FPGAs are used to implement many common embedded functions other than security.
Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.
The UltraScale™ architecture combines a successful architectural platform with numerous innovations and second-generation 3D IC technology to deliver breakthrough system performance, unprecedented capacity, and lower power. Based on the industry's first ASIC-class programmable architecture, Kintex® UltraScale and Virtex® UltraScale devices are enabling system OEMs to build smarter systems with fewer devices…faster. Read this white paper to learn more.
If you ever had to make the tough decision between performance and power, watch this webcast. Our Arria® V FPGAs have been optimized to ensure you have the performance you need at the lowest power. Get insight into the Arria V FPGA architecture, the I/O and transceiver capability, and how we help you reduce the cost of your entire system.
In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.
SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA) devices support advanced high performance bus (AHB) bus as a multi-layer AHB matrix. SmartFusion2 SoC FPGA devices AHB bus matrix has ten masters and seven direct slaves. This application note describes how to configure the weight values dynamically for the AHB bus matrix masters to access the AHB bus matrix slave using the weighted round-robin (WRR) arbitration. This application note also provides a reference design with two fabric masters connected to the FIC_0 and FIC_1 interfaces. The two fabric masters can access a single slave eSRAM1 using the WRR arbitration.
Are you interested in the new generation of high-speed ADCs with serial interfaces? Do you believe that gigabit serial interfaces are complex? Watch this 5-minute video to see how easy it is to interface Linear Technology’s high-speed ADCs to Altera’s embedded transceiver FPGAs.
This white paper identifies the drivers behind the migration to 100G interfaces, and shows how to leverage FPGAs to implement this high-speed interface. The emerging 40GbE and 100GbE standards for data center and core network systems rely heavily on FPGAs to share those sectors with other protocol infrastructures. In addition to providing an unprecedented amount of resources such as logic, on-chip memory, and DSP blocks, Altera Stratix IV devices are the only FPGA family to enable these designs.
In-System Programming (ISP) can be used to reprogram design iterations and field upgrades. SmartFusion®2 SoC FPGA devices support ISP using the Universal Asynchronous Receiver/Transmitter (UART) interface. This document describes how to program the following, using ISP through the UART interface: • embedded Non-volatile Memory (eNVM) • FPGA Fabric • both the eNVM and the FPGA Fabric For more information on programming SmartFusion2 SoC FPGAs, see the SmartFusion2 Programming User's Guide. For information on system controller programming services, see the SmartFusion2 System Controller User's Guide.
This white paper shows the feasibility of implementing the digital processing portion of a representative radar system using low-cost Cyclone® V SoC FPGAs. Advantages of this approach compared to a custom ASIC are reduced time to market, field upgradability, the ability to rapidly and easily implement in ARM® Cortex™-A9 microprocessor systems, and available automotive-grade devices.
When implementing high-bandwidth PCI Express® (PCIe®) designs on FPGAs, success is never guaranteed. You want to spend your time creating custom logic that differentiates your design in the marketplace, not doing tedious work like manually wiring up all the components. Get your design to market faster and with less effort by using tools that free you up to complete the creative design work. These innovations will help you avoid the complexities of PCIe implementation, such as Transaction Layer Packet encoding and decoding, along with the mundane tasks of system integration like width matching, clock domain conversion, and arbitration. This way, you can dramatically shorten your FPGA design and verification cycles, meet performance requirements, and increase your overall design productivity.
In this episode of Chalk TalkHD Amelia chats with Louie de Luna about Aldec's new Spec-TRACER tool and how Spec-TRACER helps you navigate your way through your design flow - from beginning to end, from requirements to verification.
High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently addressing the subsequent increase in system bandwidth by attaining higher data rates and achieving greater integration is becoming an ever-greater challenge. This challenge includes targeting lower bit error ratios (BERs) and ensuring signal and power integrity while maintaining power efficiency and optimizing design productivity. This white paper explores transceiver architecture in Altera® 28nm FPGAs for applications at 10 to 28 Gbps, and highlights the architectural advantages for making high performance systems with low BER.