Increased capability does not have to increase your cost. Arria V FPGAs provide the highest bandwidth and the most hard IP at the lowest price. In addition, by designing with Arria V FPGAs, you can save system costs, operating costs, and manufacturing costs.
Increasing industry demand to deliver HD video channels requires studio equipment providers to deliver integrated products that provide the required bandwidth and processing power, while minimizing cost and power. This paper describes how Altera’s 40-nm and 28-nm FPGAs are tailored to help deliver highly-integrated, HD studio equipment products. The paper provides an analysis of the performance requirements, resource utilization, and power consumption characteristics for the format conversion of multiple video channels.
In the past decade, the size and complexity of many FPGA designs exceeds the time and resources available to most design teams, making the use and reuse of Intellectual Property (IP) imperative. However, integrating numerous IP blocks acquired from both internal and external sources can be a daunting challenge that often extends, rather than shortens, design time. As today's designs integrate increasing amounts of functionality, it is vital that designers have access to proven, up-to-date IP from reliable sources.
Over 70% of designs on Altera® FPGAs require some type of external memory in the design, but the needs vary depending on the individual application. This white paper addresses all aspects of building external memory solutions with Altera FPGAs, including application needs, memory capabilities of Altera FPGAs, and device and IP selection. Also discussed is the modular style of the memory components, comprised of Altera’s controller and PHY offerings with circuit and calibration features.
Designing video equipment for streaming multiple uncompressed video signals is a new challenge, especially with the demand for high-definition video streams. This white paper examines how a multichannel streaming PCIe DMA controller and other “building block” IP cores are combined within a Cyclone IV GX FPGA to support SD- and HD-SDI applications using an open-source video packet streaming-format protocol such as those used in non-linear editors, video servers, and video-capture applications.
Current market trends in video surveillance present a number of challenges to be addressed, including the move from analog to digital cameras, conversion to high-definition (HD) video, adoption of Wide Dynamic Range (WDR) sensors, and Internet Protocol (IP) connectivity for control and data streams. This white paper describes the IP Surveillance Camera Reference Design and shows how the entire system is built using a low-cost Altera® Cyclone® III FPGA
Do you worry about security in your FPGA design? Are there bad guys out there trying to take advantage of security holes in your electronic designs? What can we do to stop them? In this episode of Chalk Talk, Amelia chats with Tim Morin (Microsemi) about the practical aspects of security in mainstream SoC FPGAs - what threats are out there and what we can all do to help keep the bad guys at bay.
Whether the need is for quieter blower fans in air conditioning systems, or greater efficiency under dynamically changing load conditions for an electric car drive-train, performance and cost goals for permanent magnet synchronous motor (PMSM or BLDC) controllers become more challenging by the day.
Sr. Defense Architect Jim Anderson shows how Xilinx defense-grade Virtex FPGAs enable the highest level of information assurance with Type-1 Single-chip Cryptography in a UAV application.
This white paper examines the impact of transistor design transitions in the semiconductor manufacturing industry from traditional planar to 3-D structures, and how it will provide a significant boost in high-performance programmable logic speed, power, and production availability. This paper also provides a background on the development and state of Tri-Gate technology and accesses the benefits of Tri-Gate technology through Altera® FPGAs.
FPGAs are becoming one of the most important facets of basestation architectures, and so the spotlight has fallen on them to minimize power consumption. To minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, the ECP3’s static power consumption was reduced by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs.
A history of architectural and process advancements has enabled Altera® Cyclone® V FPGAs to be used in numerous low-cost and low-power applications in the industrial, automotive, military, communication and consumer markets, among others. This white paper outlines a real-life PCI Express® (PCIe®) Gen1x4 reference design including a DDR3 memory controller. It shows just how effective Cyclone V FPGAs are in minimizing total system cost while achieving performance and power targets.
Sponsored by: Altera
When developing a multi-FPGA prototype of an ASIC or SOC, you have many decisions to make: how to distribute clocks; where to put the daughter boards with real-world interfaces; which modules should be assigned to each FPGA; where and how many cables connect the FPGAs; and how to squeeze all the signals into those cables. All these decisions need to result in the fastest possible prototype that you can build and debug in the allotted time. And every week the RTL changes, and sometimes it seems that every decision you make forces you to revisit all the decisions that came before.There is a better way.
Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs.
For broadcast and Pro A/V applications, PCI Express (PCIe) Gen2 offers the increased bandwidth needed to support the move to 1080p60 content and enables video applications to follow the IT industry’s transition to the new standard. This webcast discusses Altera’s 4-channel solution for bridging 3G Triple-Rate SDI to PCIe Gen2.