In this episode of Chalk TalkHD Amelia chats with Tom Hill of Xilinx about their new Kintex-7 DSP development kits that will finally get you onto the rocket-coaster of FPGA-powered DSP.
This white paper shows the feasibility of implementing the digital processing portion of a representative radar system using low-cost Cyclone® V SoC FPGAs. Advantages of this approach compared to a custom ASIC are reduced time to market, field upgradability, the ability to rapidly and easily implement in ARM® Cortex™-A9 microprocessor systems, and available automotive-grade devices.
Get an initial look at the industry’s first 28-nm high-end FPGA. In our Stratix® V FPGAs, you’ll get devices featuring: An industry-record 3.9 billion transistors, One million logic elements, Integrated transceivers with data rates up to 28 Gbps and an abundance of hard intellectual property (IP) blocks. Samples are shipping now. Watch this 3-minute video to see the progress of our silicon checkout process, as well as 14.1-Gbps transceiver performance.
FPGAs are increasingly replacing electronic components used for industrial applications, thus international standards like the IEC 61508 have to support these evolving technology trends if they want to keep their relevance. This white paper gives developers eight simple reasons why FPGAs should be chosen in their IEC 61508 functional safety project versus standard microcontrollers or DSPs.
Join Dr. Howard Johnson and Jack Carrel, Senior Staff Application Engineer from Xilinx as they review the new Virtex-7 HT FPGA family from Xilinx.
The Xilinx Documentation Navigator helps customers find the information they need quickly, ensures customers are always reading the latest information, and offers single-click download management. This short video provides an overview of the Xilinx Documentation Navigator.
This video shows a quick lab demo of the Virtex-6HXT, the industry's highest bandwidth FPGA, featuring 24GTH transceivers (11+Gb/s) AND GTX transceivers (6.6Gb/s) for a total of 72 Transceivers. This FPGA combines the world's highest performance FPGA fabric with the world's highest performance serial transceivers, sampling now! Please subscribe and stay tuned for future demos of our superior performance and exclusive compliance to a variety of optical specs.
FPGA applications are demanding higher memory bandwidth and greater performance. To meet these requirements, we offer external memory solutions that are faster, better, and easier to use.
This video showcases TimingDesigner capabilities, especially for building complex diagrams. It will cover derived clocks, derived signals, and differentially ended signals which will include state decodes, measure events, guarantees and skews. Lastly it will cover complex diagram capabilities in the parameter spreadsheet.
This application note describes a parameterizable content-addressable memory (CAM), and is accompanied by a reference design that replaces the CAM core previously delivered through the CORE Generator™ software. The CAM reference design should be used for all new FPGA designs targeting Virtex®-6, Virtex-5, Virtex-4, Spartan®-6, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP FPGAs, and newer architectures. All the features and interfaces included in the reference design are backward compatible with the LogiCORE™ IP CAM v6.1 core. In addition, because the reference design is provided in plain-text VHDL format, the implementation of the function is fully visible, allowing for easy debug and modification of the code.
This video features stacked silicon interconnect technology and how it is implemented in the ISE design suite. Liam Madden, VP of Silicon Technology explains...
This paper will enumerate the benefits of a platform-based system design approach. The original electronic design process built by linking tools together has remained largely unchanged for decades (i.e. tool-chains). A layered platform architecture unifies PCB, FPGA and embedded software development into one application. At the foundation is a unified data model that enables numerous data management benefits including versioning and ECO management. Companies switching to a platform based design process are doubling their productivity as compared to traditional tool-chains.
Learn how to run simulation with ZYNQ® BFM IPI design using Synopsys VCS simulator in Vivado®. We will provide a demonstration on how to compile simulation libraries, generate simulation scripts for an IP or an entire project and then run simulation.
Xilinx is multiplying the value of 20nm with the UltraScale™ architecture and associated family of FPGAs and 3D ICs. Whether viewed from almost every attribute at the chip level or viewed when integrating multiple chips into one or fewer chips at the system level, you will find compelling value metrics as you migrate to an UltraScale solution. UltraScale architecture and Vivado® Design Suite are co-optimized to enable a device utilization target of 90%, which can result in up to a 30% effective cost advantage for the next generation of smarter, high performance systems in: Packet processing: Multi-hundred gigabit throughput Waveform processing: Multi-teraMAC throughput Image and video processing: 8K4K image and video processing and transport High performance computing: Multi-teraflop throughput Learn More about potential chip and system level value multipliers.