Part 2 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews implementation challenges and how SDSoC helps solve those challenges, take a fully implemented design and modifying it to further optimize the accelerated functions. Then reviews how SDSoC enables interactive debug on an implemented design running on an evaluation board.
The UltraScale™ architecture provides numerous technical innovations to exceed the utilization and performance demands of next-generation applications, all while offering both architectural migration and package footprint migration for optimal design reuse.
In this Chalk TalkHD Amelia talks to David Schmidt of Arrow about the new Intel Atom™ processor with an Altera Arria FPGA built right into the package.
This application note describes a parameterizable content-addressable memory (CAM), and is accompanied by a reference design that replaces the CAM core previously delivered through the CORE Generator™ software. The CAM reference design should be used for all new FPGA designs targeting Virtex®-6, Virtex-5, Virtex-4, Spartan®-6, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP FPGAs, and newer architectures. All the features and interfaces included in the reference design are backward compatible with the LogiCORE™ IP CAM v6.1 core. In addition, because the reference design is provided in plain-text VHDL format, the implementation of the function is fully visible, allowing for easy debug and modification of the code.
Vidya Rajagopalan, VP of Processing Platforms at Xilinx, and Dipesh Patel, VP of Technology, Physical IP Division at ARM, introduce the Zynq-7000 Extensible Processing Platform from Xilinx. This new class of product combines an industry-standard ARM® dual-core Cortex™-A9 MPCore™ processing system with Xilinx unified 28nm architecture.
David Ackroyd, Business Development Director for OmniTek demonstrates an an Ultra 4K Tool Box that includes conversions from 4K to/from SD including quad 3G-SDI.
This video features a hardware setup of a test vehicle of stacked silicon interconnect technology. Liam Madden, VP of Silicon Technology at Xilinx explains...
Today, the cool kids aren’t using discrete components for power anymore. Nope. They’re using power modules. In this episode of Chalk TalkHD Amelia chats with Rich Nowakowski and Kevin Beals (Texas Instruments) about power modules, and why they’re the best solution for a wide range of design projects.
Learn how to run simulation with MicrBlaze™ IPI design using Synopsys VCS simulator in Vivado®. We will provide a demonstration on how to compile simulation libraries, generate simulation scripts for an IP or an entire project and then run simulation.
This video demonstrates how to create a simple image processing pipeline to detect motion, and to insert motion-edges into a live HD 1080p video stream running at 60 frames per second.
One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.
The UltraScale™ architecture introduces many innovations over traditional FPGA architectures that increase performance and reduce power consumption. In this video, we will focus on enhancements to the routing, logic and implementation software that result in an architecture allowing for the device to be highly utilized while still maintaining performance, and keeping runtime low.
This video features stacked silicon interconnect technology and how it is implemented in the ISE design suite. Liam Madden, VP of Silicon Technology explains...