The combination of Altera’s Arria II GX family and TPACK’s 2.5-Gbps/10-Gbps Ethernet-over-SONET/SDH and 10-Gbps/20-Gbps switch/NPU solutions meet the requirements of next-generation MSPP linecards and maintain existing infrastructure. Like ASSPs, FPGAs are based on the traditional manufacturing process, either in-house or via commercial foundries, but due to their broader and more generic application, the production volume that FPGAs attain justifies investment in the latest manufacturing processes and technology.
While general-purpose graphics processing units (GP-GPUs) offer high rates of peak floating-point operations per second (FLOPs), FPGAs now offer competing levels of floating-point processing. Moreover, Altera® FPGAs now support OpenCL™, a leading programming language used with GPUs.
Xilinx FPGAs offer a low cost, but flexible solution to meet multiple end customer requirements for differing levels of complexity in Automotive Instrumentation Design.
As serial data rates increase beyond 10 Gbps to address high-bandwidth applications (e.g., 40G/100G systems), board design challenges grow as well. Ensuring statistical reliability of a serializer/deserializer (SERDES) channel requires careful board design, as well as advanced silicon capabilities to handle losses due to PCB material properties and reflections due to discontinuities in the channel.
This white paper summarizes performance as measured on the Spartan-6 FPGA Connectivity targeted reference design available with the Spartan-6 FPGA Connectivity Kit. The results clearly demonstrate that: Throughput scales with variation in packet size, ,PCI Express performance improves with higher maximum payload size, CPU utilization improves with checksum offloading, An inverse relationship exists between packet size and CPU utilization.
The SoC FPGA design is a new device that incorporates both FPGA and microcontroller subsystem on a single device. As these devices capabilities extend to high speed serial and DDR memory interfaces, and high performance FPGA fabric with DSP processing, the architecture within the device requires an advanced tool methodology to simplify the designer’s experience and accelerate time-to-market. System Builder accomplishes this by guiding users visually, presenting a high level abstraction for construction and then generating a “correct by construction” implementation of the system components.
The availability of devices incorporating hardened ARM® applications processors closely coupled to an on-chip FPGA fabric opens a world of possibilities to electronic system designers. However, these devices also introduce novel design, debug, and optimization challenges. New development methodologies are required to address software and hardware integration issues and system-level performance optimizations efficiently at a price affordable by small- and medium-sized companies. This white paper outlines Altera and ARM’s latest innovations in on-chip debug logic, FPGAs, and software debug and analysis tools aimed to address these challenges.
This white paper describes how Altera’s 28nm devices enable product developers to control power consumption in today’s increasingly power sensitive applications.
The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.
When developing and maintaining industrial communications hardware, supporting new or additional industrial Ethernet protocols often requires new hardware and corresponding software stacks. Rather than re-spinning your boards and migrating software code, you can save time and resources by choosing FPGAs.
Watch demonstration of the second device in the Xilinx 28nm FPGA family -- the high performance Virtex-7 XV485T.
As industrial system complexity increases, FPGAs offer the ability to integrate an entire system on a chip (SoC), at a lower cost compared to discrete MCU, DSP, ASSP, or ASIC solutions. This document describes using an Altera industrial-grade FPGA as a coprocessor or SoC to bring flexibility to industrial applications. Providing a single, highly integrated platform for multiple industrial products, Altera FPGAs can substantially reduce development time and risk.
Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.
Extending the Spartan-6 FPGA Connectivity TRD (PCIe-DMA-DDR3-GbE) to Support the Aurora 8B/10B Serial Protocol
Targeted Reference Designs (TRDs) provide Xilinx designers with turn-key platforms to create FPGA based solutions in a wide variety of industries. This application note extends the Spartan-6 FPGA PCIe-DMA-DDR3-GbE TRD to support Aurora 8B/10B serial protocol.
Customers have prototyped their products utilizing Microsemi FPGA & cSoCs and then quickly went to production on the same platform. This ensures design consistency and gets product to their customers on time as scheduled. Microsemi’s private label program goes a step further and provides the ability to custom mark devices with company logo’s and part numbers. Furthermore, our devices do not require an external EEPROM for boot-up configuration, thus the end product can be sold as single IC solution. This approach provides numerous levels of security including prevention of reverse engineering coupled with 128-bit encryption keys to unlock and reprogram your device for field upgradability when the need arises.