Injecting Automation into Verification – Improved Throughput

This webinar will focus on the highest value tools and techniques for improving test stimulus, debug effectiveness and simulation throughput. One of the most common verification process improvement opportunities is being able to more easily create test cases, including leveraging standard bus interfaces like PCIe for stimulating your system. We will also describe common techniques for improving simulation performance.

Power Reduction in Next-Generation UltraScale Architecture

Designed to scale from 20 nm planar technology through 16 nm FinFET and beyond, Xilinx UltraScale™ devices equip an already-successful architectural platform with numerous innovative power reduction techniques. This white paper explores the challenges of managing power efficiently, reducing device power requirements, and innovating new power solutions at the speed of Moore's law.

National Instruments Comments on Xilinx Extensible Processing Platform

Xilinx Extensible Processing Platform testimonial from customer National Instruments.

SDAccel Development Environment Demonstration

This video demonstrates the SDAccel™ development environment for acceleration using a standard X86_64 workstation containing an Alpha data ADM-PCIE-7V3 accelerator.

Xilinx Documentation Navigator Overview

The Xilinx Documentation Navigator helps customers find the information they need quickly, ensures customers are always reading the latest information, and offers single-click download management. This short video provides an overview of the Xilinx Documentation Navigator.

Successfully Designing FPGA-Based Systems

One key challenge in successfully designing FPGA-based systems is choosing the right FPGA for the design needs, and maximizing the use of FPGA resources. In this paper Cadence offers recommendations for power-supply connections, pin selections and assignments, and other tips and methodologies to help customers design high-quality FPGA-based systems.

Simulating Zynq BFM design using Synopsys VCS in Vivado

Learn how to run simulation with ZYNQ® BFM IPI design using Synopsys VCS simulator in Vivado®. We will provide a demonstration on how to compile simulation libraries, generate simulation scripts for an IP or an entire project and then run simulation.

Advanced Timing Exception Multicycle Path Constraints

Learn Xilinx recommendations for constraining multicycle path constraints. Understand and apply multicycle path exception constraints in your design.

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

Artix-7 FPGA Transceiver: The Industry's Most Capable Transceiver in a Low-End Device

In this video you’ll see the FPGA industry’s only low end transceiver solution—the Artix-7 FPGA transceiver—that provides auto-adaptive equalization, 2D Eye Scan, and IBIS-AMI simulation models to simplify high speed serial design for cost-sensitive applications.

FPGA Reliability and the Sunspot Cycle (REVISED)

What if your design had to go close to the sun? Would you be comfortable? Engineers design for system-level reliability when creating complex electronic systems. System reliability is dependent on a number of factors, including the reliability of the individual semiconductor devices selected for each design. Radiation effects impact device reliability in terrestrial as well as space applications. By choosing FPGA components judiciously, designers can significantly enhance the operational reliability and stability of any system.

Advanced Timing Exception Multicycle Path Constraints

Learn a little about the different types of exception constraints followed-up by a detailed look at the false path, min/max delay and case analysis constraints. We'll also review exception priority and a few tips for constraining exceptions constraints.

Industry’s 1st Single Chip 400GE Solution

Watch a demonstration of the industry’s first single chip solution for 400G applications, featuring the 20 nm Virtex® UltraScale™ device interfacing to Sumitomo Electric CFP4 optical modules and 10 km of optical fiber.

Why Do I Need a Customizable ARM-based SoC?

In this episode of Chalk TalkHD Amelia chats with Todd Koelling of Altera about what’s inside these new SoC FPGAs and how you can get started designing with them.

Virtex-6HXT Lab Demo

This video shows a quick lab demo of the Virtex-6HXT, the industry's highest bandwidth FPGA, featuring 24GTH transceivers (11+Gb/s) AND GTX transceivers (6.6Gb/s) for a total of 72 Transceivers. This FPGA combines the world's highest performance FPGA fabric with the world's highest performance serial transceivers, sampling now! Please subscribe and stay tuned for future demos of our superior performance and exclusive compliance to a variety of optical specs.

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