Across applications, the two most common functions implemented in FPGA-based high-performance signal processing are FIR filters and FFTs. The FPGA’s DSP architecture must be optimized to allow the most efficient implementation of these structures as this directly translates into cost and power benefits to the customer. This paper introduces the DSP architecture of the latest 28nm Altera® FPGAs and shows how this architecture enables the most efficient implementation of FIR filters and FFTs.
The whole point of an FPGA is flexibility. We could also mention integration and say instead that the whole point of an FPGA is flexibility and integration. But then there is cost savings. So the whole point of an FPGA is flexibility, integration and cost savings. Yet there is also power reduction. And then there’s security.
Did you know that you can build a flexible and scalable motor control system in a single FPGA? Watch this 6-minute video to: Learn about the 4 reasons why FPGAs are right for motor control? How implementing a simple feedback mechanism can synchronize two motors, Leverage versatile design tools such as our Qsys integration tool for a scalable motor control solution, See two demonstrations of the BeMicro SDK-based Motor Control Kit (BeInMotion).
Now there’s a 100 percent MIPS-compatible soft processor available just for Altera® FPGAs and HardCopy® ASICs. The MP32 is also the industry’s first soft processor that runs the VxWorks operating system. Watch this 10-minute video to learn five reasons why you should use MP32 in your next custom embedded design.
Learn how Vivado IP Integrator can be used to rapidly build a video sensor processing pipeline design using AXI4, a MicroBlaze processor and an external DDR3 memory interface. Vivado IP Integrator can be used to quickly build and reuse IP and IP subsystems. Watch the video now to learn more!
New All Programmable Abstractions initiative improves productivity of hardware designers and empowers systems and software developers to directly leverage Xilinx All Programmable devices.
Software simulation of RTL is no longer capable of providing all of the verification required for today's complex ASIC designs. Modern ASICs are a complex mixture of hardware and software, so it is necessary to verify the design within the context of the complete system, running the full range of software at speeds that approach real-time. Successfully validating an ASIC design on an FPGA-based prototype before committing to silicon is now a key project milestone for most design teams. This paper examines some of the best practices for both successful bring-up and logic debug of ASICs using FPGA-based prototypes.
Accelerating the development of smarter systems requires levels of automation that go beyond RTL-level design. With the introduction of the Vivado™ Design Suite 2013.1, Xilinx delivers a SoC-strength, IP- and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation.
Because a fast and robust memory interface is crucial for many designers, Altera provides the fastest, most efficient, and lowest latency memory controllers, which allow designers to work with today’s higher speed memories quickly and easily. Designing with Arria V FPGAs not only helps to make designs successful but also ensures that implementation is fast and easy.
In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.
Automotive electronics designers have been turning more frequently to programmable logic solutions to meet the needs of their next generation designs. FPGAs offer time-to-market benefits along with simplified qualification and greater flexibility in comparison to historic ASIC-based solutions.
In the past decade, the size and complexity of many FPGA designs exceeds the time and resources available to most design teams, making the use and reuse of Intellectual Property (IP) imperative. However, integrating numerous IP blocks acquired from both internal and external sources can be a daunting challenge that often extends, rather than shortens, design time. As today's designs integrate increasing amounts of functionality, it is vital that designers have access to proven, up-to-date IP from reliable sources.
Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency
The programmable imperative—the critical need to achieve more with less, to reduce risks wherever possible, and to quickly create differentiated products using programmable hardware design platforms—is driving the search for FPGA-based solutions that provide the capacity, lower power, and higher bandwidth with which users can create the system-level functionality currently delivered by ASICs and ASSPs. Download this whitepaper to learn more.
Advanced analytics is replacing simple motion detection in surveillance cameras. See how you can get 1080p high-definition (HD) analytics in your IP camera with a single-chip video analytics solution.
Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.