Xilinx offers a robust and extensive infrastructure that enables Zynq®-7000 SoC users to be more productive and get their designs to market quickly. The Vivado®-HLS or high level synthesis tool allows designers to make architectural tradeoffs rapidly and develop highly optimized systems in the Zynq-7000 device. The Zynq-7000 platform also includes support for today’s most popular software design environments and Xilinx offers a proven portfolio of IP, design kits and reference designs.
Ian Ferguson, VP of Segment Marketing at ARM, explains how an ARM processor combined with an FPGA addresses the embedded space. He also discusses three areas where programmable logic provides the most value along with the new markets addressed by the Zynq®-7000 All Programmable device.
Sr. Defense Architect Jim Anderson shows how Xilinx defense-grade Virtex FPGAs enable the highest level of information assurance with Type-1 Single-chip Cryptography in a UAV application.
This white paper discusses Altera’s programmable system-on-chip (SoC) approach to ARM-based embedded system implementation. The single-chip approach can be of particular value to embedded systems developers facing stringent time-to-market, cost, performance, design reuse, and longevity requirements.
Advanced analytics is replacing simple motion detection in surveillance cameras. See how you can get 1080p high-definition (HD) analytics in your IP camera with a single-chip video analytics solution.
SoC FPGAs are a powerful new class of programmable devices that are applicable to a wide range of electronic designs. This white paper discussed a number of criteria to select the best SoC FPGA for your particular application, including system performance, design reliability and flexibility, system cost, power consumption, future product roadmaps, and the important role that development tools will play into the success of these SoC FPGAs.
Systems with high speed serial links often have serial channels which result in signal distortion described as insertion loss, reflection, cross-talk, and other channel impairments. Receiver equalization can help compensate for such channel-driven losses and distortions, but link tuning and bring-up can be non-trivial even for the most experienced transceiver and signal integrity specialists. Learn how Xilinx FPGAs with fully auto-adaptive equalization is critical to high speed transceiver design and enables system designers to get their systems up and running quickly.
While supporting increasingly demanding bandwidth requirements, your products also need to meet stringent cost and power budgets. Altera's new 28-nm Stratix® V FPGAs and HardCopy® V ASICs deliver groundbreaking innovations addressing the challenges of next-generation designs.
High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently addressing the subsequent increase in system bandwidth by attaining higher data rates and achieving greater integration is becoming an ever-greater challenge. This challenge includes targeting lower bit error ratios (BERs) and ensuring signal and power integrity while maintaining power efficiency and optimizing design productivity. This white paper explores transceiver architecture in Altera® 28nm FPGAs for applications at 10 to 28 Gbps, and highlights the architectural advantages for making high performance systems with low BER.
Introspect Technology has implemented its award-winning Introspect ESP embedded signal integrity analyzer on Altera’s high-end 28nm transceiver FPGAs. The result was a game-changing ability to achieve link optimization and interoperability on complex system boards containing a multitude of SerDes links. This white paper describes the various Introspect and Altera® technologies involved and illustrates, with real-life examples, the ability to self-measure, self-optimize, and self-repair SerDes links and systems.
In this white paper, Acceleware introduces parallel programming targeting Altera® FPGAs using the OpenCL™ framework to graphics processing unit (GPU) programmers. This white paper provides a brief overview of OpenCL, discusses the Altera FPGA architecture and its benefits, and explains how OpenCL kernels are executed and optimized on FPGAs versus GPUs.
With today’s high-bandwidth, low-latency devices and associated applications—such as smart phones, tablets, HDTV, and 3DTV—computer and network system vendors endeavor to deliver systems that don’t significantly add to network or internet traffic congestion and latency. This document discusses how optical interface technology embedded in an FPGA overcomes the reach, power, port density, cost, and circuit board complexity challenges associated with discrete copper interconnects.
This white paper discusses the major challenges associated with accurately predicting power consumption in FPGAs, namely, obtaining accurate signal activities, static power modeling, and dynamic power modeling, as well as how Altera addresses these challenges through the PowerPlay early power estimator and the Quartus® II PowerPlay power analyzer. This paper also presents the accuracy of the model by comparing predicted power consumption with actual silicon measurements using an extensive suite of real-world customer designs. Using these best-in-class power analysis tools, a designer can model the power consumption of their design to within, on average, ±10% accuracy when used with accurate design information.
Xilinx's Agile Mixed Signal technology offers a better way to scale and customize common analog interfaces requirements.
RAID adapter cards are critical data-center subsystem components that ensure data storage and recovery during power outages. Battery-backed designs have hazardous waste disposal, shelf life, and maintenance issues, but recent advances in FPGA and flash-memory technologies support lower power memory backup designs that are powered by ultra capacitors. This paper provides an overview of the supporting component technologies that support such environmentally-friendly data recovery solutions.