In this episode of Chalk TalkHD Amelia Dalton talks to David Flowers from Microchip about creating tablet and smartphone accessories - and how it just may be easier than you think...
High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently addressing the subsequent increase in system bandwidth by attaining higher data rates and achieving greater integration is becoming an ever-greater challenge. This challenge includes targeting lower bit error ratios (BERs) and ensuring signal and power integrity while maintaining power efficiency and optimizing design productivity. This white paper explores transceiver architecture in Altera® 28nm FPGAs for applications at 10 to 28 Gbps, and highlights the architectural advantages for making high performance systems with low BER.
FPGAs are becoming one of the most important facets of basestation architectures, and so the spotlight has fallen on them to minimize power consumption. To minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, the ECP3’s static power consumption was reduced by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs.
Lattice Semiconductor has developed and supported a number of reference designs for display interfaces in various devices. A display interface is now available in the MachXO2 PLD family. Because this interface is now supported in MachXO2 devices, designers have an even lower cost and very low power alternative to implement embedded displays. As described in this white paper, the MachXO2 provides a compelling choice for this application.
Utilizing the Khronos Group’s OpenCL™ standard on an FPGA may offer significantly higher performance and at much lower power than is available today from hardware architectures such as CPUs, graphics processing units (GPUs), and digital signal processing (DSP) units. In addition, an FPGA-based heterogeneous system (CPU + FPGA) using the OpenCL standard has a significant time-to-market advantage compared to traditional FPGA development using lower level hardware description languages (HDLs) such as Verilog or VHDL.
In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.
7 series 10GBASE-KR LogiCore™ IP have achieved 100% protocol conformance to the 10GBASE-KR standard. In this video you'll see a 10 Gigabit Ethernet MAC with frame generator connected to the 10GBASE-KR PHY IP, operating over a backplane environment.
With applications needing to store more data for longer periods of time, SATA provides an efficient, cost-effective storage interface. Watch this 7-minute video for a demo showing how easy it is to take advantage of the data storage capabilities of SATA using 40-nm transceiver FPGAs.
In the past, FPGA vendors commonly segmented their portfolios between "high-end" and "low-cost" devices. However, as developers have refined the way they leverage FPGA technologies, they have voiced the need for a "mid-range" solution, featuring high-end functionality and performance in a cost effective package. The Xilinx® Kintex™-7 family of FPGAs was developed for these applications, delivering the most balanced power and performance in the industry while providing high-end features, such as cutting-edge transceivers, integrated IP, and extensive DSP resources.
Learn a little about the different types of exception constraints followed-up by a detailed look at the false path, min/max delay and case analysis constraints. We'll also review exception priority and a few tips for constraining exceptions constraints.
The standard that governs the design of avionic components and systems, DO-254, is one of the most poorly understood but widely applicable standards in the avionic industry.
Advanced FPGAs are difficult to characterized due to their advanced process nodes, which delays the availability of final timing models until silicon characterization is completed. This paper describes the timing models available for end-user FPGA design, in advance of production FPGAs. This paper explains the development cycle of FPGAs, along with the timing models available at each stage. This paper also describes the best practices that you can use at each stage of the timing model.
Active-HDL is an integrated FPGA Design and Simulation solution, with design entry, a high-performance mixed-language simulator and an easy-to-use, multi-vendor FPGA flow manager. Active-HDL has interfaces to over 80 leading EDA tools, making it the most powerful environment. Check out the top features and product configurations to see if Active-HDL is right for you.
The Xilinx Documentation Navigator helps customers find the information they need quickly, ensures customers are always reading the latest information, and offers single-click download management. This short video provides an overview of the Xilinx Documentation Navigator.
In this episode of Chalk TalkHD Amelia chats with Suhel Dhanani of Altera about the who, what, and how of industrial ethernet design.