This free eBook provides technical details and design considerations for implementing the common circuit board power management functions. This book also provides generalized cost effective solutions for each of these functions that can be customized to meet a circuit board’s specific voltage, current and control environment.
High-level design methods can dramatically increase your productivity. Now that technologies like high-level synthesis (HLS) have gone mainstream, we can make some serious improvements to our FPGA design process. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven of Xilinx about how the new HLx editions of Vivado Design suite are taking high-level design mainstream.
There is a significant gap between FPGA on-chip memories and off-chip memories that causes problems in some applications. What we need to fill that gap are much larger on-chip memory resources to fill that need. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the new UltraRAM blocks in Xilinx FPGAs and Zynq MPSoCs.
Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.
Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.
Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.
USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.
New SoCs like the Xilinx Zynq are changing the industry - with new levels of functionality, flexibility, performance, and power efficiency. But, to take advantage of this new technology you'll need connectivity solutions that are up to the task. In this episode of Chalk Talk, Amelia Dalton chats with Mark Bell from TE Connectivity about plugs, connectors, antennas, and other connectivity solutions for today's most demanding designs.
Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.
You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.
For industrial-grade applications, consumer-style connectors just don't cut it. You'd never use RJ45 where you really care about ruggedness or reliability. In this episode of Chalk Talk, Amelia Dalton chats with Tom Wess of TE Connectivity about M8 and M12 high-reliability connectivity solutions that will keep your system operating smoothly under harsh conditions.
In this episode of Chalk TalkHD Amelia chats with Suhel Dhanani of Altera about the who, what, and how of industrial ethernet design.
Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.