A Safety Methodology for ADAS Designs in FPGAs

Advanced Driver Assistance Systems (ADAS) are the next wave of innovations to make driving on our more and more congested roads safer. This white paper discusses the use of Altera(r) FPGAs in safety-critical ADAS that have better performance requirements than commercial off-the-shelf (COTS) products. It looks at the general safety concept of such applications and provides examples on how to implement certain diagnostics in the FPGA to detect faults in the application.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

MachXO2 Infomercial

This video spoof is on the lighter side of Lattice. If you haven’t seen this MachXO2 video yet, check it out. You might even chuckle a bit or at least learn a new way to keep warm and toasty in the lab.

Injecting Automation into Verification – Improved Throughput

This webinar will focus on the highest value tools and techniques for improving test stimulus, debug effectiveness and simulation throughput. One of the most common verification process improvement opportunities is being able to more easily create test cases, including leveraging standard bus interfaces like PCIe for stimulating your system. We will also describe common techniques for improving simulation performance.

No Room for Error: Creating Highly Reliable, High-Availability FPGA Designs

Designers of FPGAs for military and aerospace applications need to increase the reliability and availability of their designs. This is particularly true in the case of mission-critical and safety-critical, high-reliability and high-availability FPGA design including: FPGA design and verification flows, methodologies, processes and standards, architectural and algorithmic exploration, geographically distributed design teams, IP selection and verification, DO-254 compliance and much more.

Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions

Because a fast and robust memory interface is crucial for many designers, Altera provides the fastest, most efficient, and lowest latency memory controllers, which allow designers to work with today’s higher speed memories quickly and easily. Designing with Arria V FPGAs not only helps to make designs successful but also ensures that implementation is fast and easy.

SmartFusion2 SoC FPGA SERDES Characterization Report

The Microsemi SmartFusion®2 SoC FPGA family provides a fully embedded PCI Express® Gen1/2- x1/x2/x4 Endpoint. This embedded PCI Express solution is part of the SERDESIF module which supports 4 lanes of SERDES with data rates supported up to 5Gbps. The number of SERDESIF modules on the SmartFusion2 SoC FPGA depends on the device size. The smaller devices support a single SERDESIF with a single PCI Express interface. The larger devices support up to 4 SERDESIF modules for a total of 4 PCI Express interfaces.

Actel SmartFusion: Intelligent, Innovative Integration

Actel SmartFusion™ Intelligent Mixed Signal FPGAs – Innovative, Intelligent, Integration. Introducing the only device that integrates a flash FPGA, hard ARM® Cortex™-M3-based microcontroller subsystem (MSS) and programmable analog into a complete, integrated solution. Don’t compromise your embedded design. Build the system you want, with all the features you need, on a single-chip solution. Read the White Paper to learn more.

Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design

This application note describes two reference designs that demonstrate Ethernet operations of the Altera® Triple-Speed Ethernet MegaCore® functions with on-board Marvell 88E1111 PHY chips. The reference designs provide flexible test and demonstration platforms on which you can control, test, and monitor the Ethernet operations using system loopbacks.

Using the Vivado Timing Constraint Wizard

Learn how the timing constraints wizard can be used to “completely” constrain your design. The wizard adheres to the UltraFast™ design methodology defining your clocks, clock interactions, and finally your input and output constraints. In this video, you will see the wizard transform a partially constrained design into a fully constrained design that passes timing.

Xilinx Agile Mixed Signal

In this episode of Chalk TalkHD Amelia chats with Steve Logan (Xilinx ) and they're going to tell you all about Agile Mixed Signal, and how it can dramatically improve the capabilities of your next FPGA design.

Using 10-Gbps Transceivers in 40G/100G Applications (REVISED)

This white paper identifies the drivers behind the migration to 100G interfaces, and shows how to leverage FPGAs to implement this high-speed interface. The emerging 40GbE and 100GbE standards for data center and core network systems rely heavily on FPGAs to share those sectors with other protocol infrastructures. In addition to providing an unprecedented amount of resources such as logic, on-chip memory, and DSP blocks, Altera Stratix IV devices are the only FPGA family to enable these designs.

Setting and Editing Device Properties in Vivado

Learn how to use the new configuration dialog to set and edit device properties. Understand and utilize the configuration dialog for setting and editing device properties.

A Tailored Approach to FPGA Process Selection

This white paper examines three categories of process characteristics, relates them to the internal structure of modern FPGAs, and then, in turn, looks at the impact the FPGAs have on the systems that employ them. In particular, a focus on the deployment of so-called FinFET transistors shows how Altera is exploiting Intel’s 14 nm Tri-Gate process to achieve a level of FPGA density, performance, and power efficiency not reachable at all on the planar FET roadmap.

LatticeECP3 Family

The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.

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