A Generation Ahead – Zynq-7000 Video

Xilinx Zynq®-7000 All Programmable SoCs enable extensive system level differentiation, integration, and flexibility through hardware, software, and I/O programmability. Using the Zynq-7000 platform, you can design smarter systems with tightly coupled software based control and analytics with real time hardware based processing and optimized system interfaces — with vastly lower BOM costs, lower NRE costs, lower design risk, and of course much faster time to market.

Successfully Designing FPGA-Based Systems

One key challenge in successfully designing FPGA-based systems is choosing the right FPGA for the design needs, and maximizing the use of FPGA resources. In this paper Cadence offers recommendations for power-supply connections, pin selections and assignments, and other tips and methodologies to help customers design high-quality FPGA-based systems.

SDNet Demonstration

Demonstration of a 'hitless' update in a 100Gbps per second programmable packet processing system using SDNet.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

Increased Productivity Using Team Design

Xilinx® FPGAs offer up to 2 million logic cells in capacity—and they continue to grow. Designs of this complexity usually require a team of developers, and often, a team leader, who is responsible for the synthesis and implementation of the entire design. To make matters more challenging, the developers can be located internationally, with different portions of the design developed in different locations, and even by different companies. The Xilinx Team Design flow introduced in ISE® Design Suite 13.1 focuses on solving these challenges.

Intelligent Power Management with SmartFusion Intelligent Mixed Signal FPGA

The Mixed Signal Power Manager (MPM) reference design delivers flexible power management configured using the standalone MPM PC GUI tool to bear on power sequencing and management.

Firm Error Immunity in Flash FPGAs

Radiation effects are not isolated to space electronics only, but they affect all type of electronics whether they are automotive, industrial or military and avionics. What differentiates them is the type of radiation. This webcast shows how FPGA’s interact with them and why Actel FPGAs are the best solution to mitigate these effects.

Introducing the SDSoC Development Environment

The SDSoC™ development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment.

Test Vehicle Demonstration Of Stacked Silicon Interconnect Technology

This video features a hardware setup of a test vehicle of stacked silicon interconnect technology. Liam Madden, VP of Silicon Technology at Xilinx explains...

Hardware Accelerated H.264 Video Encoding using VAAPI on the Intel® Atom™ Processor E6xx Series

The Intel® Atom™ Processor E6xx Series for the embedded devices market includes the POWERVR* VXE core that provides video encoding capabilities, allowing to encode high definition video streams in the highly compressed H.264 format with a very low main CPU utilization, releasing the general purpose processor for other parallel workloads. This processor feature is available to application developers by means of the open Video Acceleration API (VAAPI [1]). This paper explains how the VAAPI can be applied to a real time video encoding task, explaining the VAAPI function calls flow, and the corresponding parameters.

Designing with Vivado IP Integrator

Learn how Vivado® IP Integrator can be used to rapidly connect a Zynq® processor to the programmable fabric. Using built in board aware design rule checks and designer automation, Vivado can greatly improve user productivity.

Allegro FPGA System Planner

The Cadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin count FPGAs on the PCB board. By replacing manual error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates physical design iterations while speeding optimum pin assignment.

Scaling Up to TeraFLOPs Performance with the Virtex-7 Family and High-Level Synthesis

This white paper provides an overview of fixed- and floating-point DSP coding techniques, ranging from RTL to the Xilinx portfolio of IP and tools. It also describes advances with High-Level Synthesis (HLS) tools, like AutoPilot, how FPGA designs can benefit from coding in a “natural language” like C or C++, and how easily FPGAs can be programmed by a large community of software programmers.

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