This white paper explores Altera’s low-power FPGA platform and the video design solutions that address the military’s complex, power-budget-constrained EO/IR design challenges and significantly increase designer productivity. Many of today’s electro-optical/infrared (EO/IR) systems require high-complexity, real-time video processing within a constrained power budget. The latest low-power, low-cost FPGA families are ideal for developing the next generation displa and EO/IR systems.
Due to their flexibility, FPGAs play a vital role for early adopters who want to design 100G systems today, prior to the standards being ratified. Altera Stratix IV GT FPGAs solve the problem for both 100G transport and 100G Ethernet by providing integrated 11.3-Gbps transceivers in the 40-nm technology node. In addition, Stratix IV GX, Arria II GX, and Arria II GZ FPGAs, and HardCopy series ASICs satisfy many application needs in OTNs and are cost-effective platforms for high-bandwidth systems
With the hard memory controller (HMC) in Altera® Cyclone® V FPGAs, designers can maximize efficiency and flexibility, thereby achieving low power and low cost for their systems and applications. Check out the whitepaper to learn more.
Altera® Cyclone® V FPGAs help designers reduce total system cost in a number of ways. Designers benefit not only from TSMC’s 28-nm Low Power (28LP) manufacturing process, but also from the architectural decisions that have gone into the Cyclone V device family and the array of powerful productivity-enhancing tools featured in Altera’s design tool ecosystem. With Cyclone V FPGAs, customers not only enjoy the lowest cost of ownership in the industry, but the widest array of low-cost parts available—from 25K logic elements (LE) to 301K LEs—and the only 28-nm solution under 100K LEs.
This video provides an exploration of Motor Control applications using Actel's SmartFusion™ intelligent mixed signal flash FPGAs for field-oriented closed-loop motor control for brushless DC (PMSM) motors, with a closer look at your challenges and a look into the Actel motor control development kit currently in development.
Ian Ferguson, VP of Segment Marketing at ARM, introduces the Zynq®-7000 All Programmable SoC as the result of a strong partnership between ARM and Xilinx. He discusses how Zynq is opening up new markets for ARM and is alleviating the need for a multi-chip solution in many applications. Ferguson also speaks to Zynq's compatibility with leading operating systems and tools, and challenges designers to develop new and creative ways to design with a Zynq-7000 SoC.
Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency
The programmable imperative—the critical need to achieve more with less, to reduce risks wherever possible, and to quickly create differentiated products using programmable hardware design platforms—is driving the search for FPGA-based solutions that provide the capacity, lower power, and higher bandwidth with which users can create the system-level functionality currently delivered by ASICs and ASSPs. Download this whitepaper to learn more.
FPGA-based co-processing is 15X faster than traditional processor/DSP systems. Conventional system design methods face stiff challenges to meet the requirements of today’s ultra-high performance applications. This video explains how the TI OMAP/Spartan-6 FPGA Co-Processing Kit delivers breakthrough system performance by integrating and optimizing the key strengths of high performance FPGAs, system control processing, and digital signal processing, all within one single environment.
This white paper explains PCB layout guidelines for designing LVDS boards using Altera FPGAs. LVDS is a high-speed, low-voltage, low-power, and low-noise general-purpose I/O interface standard. The low-voltage swing and differential current mode outputs significantly reduce EMI and have fast edge rates that cause signal paths to act as transmission lines. Therefore, ultra-high-speed board design and differential signal theory knowledge is especially useful for designing an FPGA-based LVDS board.
FPGAs that provide multi-gigabit serial transceivers to implement high-speed serial protocols have become the platform of choice for a large and growing number of applications today. The flexibility to accommodate different protocols, line rates, and emerging standards has made the multi-gigabit serial transceiver the perfect companion to the flexible reprogrammable logic in FPGAs. However, this flexibility comes at a cost. Designing systems that incorporate high-speed serial I/O is difficult enough. Designing systems that work with multiple protocols and different line rates is even more challenging.
Accelerate your next generation factory automation design with the Spartan®-6 FPGA Industrial Ethernet Kit, jointly developed with Avnet. Walk through a demonstration of the benefits and features of the kit with Giulio Corradi, Senior System Architect
Join Dr. Howard Johnson and Jack Carrel, Senior Staff Application Engineer from Xilinx as they review the new Virtex-7 HT FPGA family from Xilinx.
The availability of devices incorporating hardened ARM® applications processors closely coupled to an on-chip FPGA fabric opens a world of possibilities to electronic system designers. However, these devices also introduce novel design, debug, and optimization challenges. New development methodologies are required to address software and hardware integration issues and system-level performance optimizations efficiently at a price affordable by small- and medium-sized companies. This white paper outlines Altera and ARM’s latest innovations in on-chip debug logic, FPGAs, and software debug and analysis tools aimed to address these challenges.
With the introduction of cutting-edge touch screen products, the demand for multi-touch user-machine interfaces is growing. Adding multi-touch to a wide variety of products—from cell phones and MP3 players to medical imaging equipment and even washing machines—may be easier than you think. This webcast shows a very cost-effective way to add multi-touch to your system using Altera’s MAX® II CPLDs and surprisingly simple IP.
The first-ever 28nm FPGA demonstrates major design functionality within the first 48 hours, including 10Gbps eye quality.