Learn about Xilinx's 4x100G Transponder Reference Design running on the VC730 OTN Test Development Platform.
In a world where attacks on electronic systems are conducted remotely, security is vital in system design. Even systems that do not have commercially confidential data now have to be designed with security in mind to prevent their core IP from being copied. In this paper, we see the two elements of electronic system security: design security and data security. Increasingly, the two depend on each other. In design security the goal is to ensure the core design is protected and that the security intent of the IP owner is followed at all times. Data security refers to security applications that the system may run.
This video focuses on drawing simple diagrams in the TimingDesigner program. The presentation covers drawing clocks, signals and buses. It then moves on to edge events, which include delays and constraints. Lastly it covers edge events and the Parameter spreadsheet where it looks at variables, functions, and shows an example of a diagram of a Sharc DSP processor.
Learn how to use the new configuration dialog to set and edit device properties. Understand and utilize the configuration dialog for setting and editing device properties.
The white paper describes Altera(r) technology leadership in the serial memory interoperability space and describes the underlying hardware platform and controller architecture used to carry out a successful interoperability between Stratix(r) V FPGA and the HMC device. The document also includes real system-level examples where HMC solution provides an alternative solution to conventional memory-based solutions.
Actel's Mixed-signal Power Manager (MPM) enables designers to control and reduce power at the system level, offering fully-verified, timing-closed, proven-in-hardware power supervision and management capabilities, while utilizing Actel Fusion mixed-signal FPGA. Watch the short webcast to learn more.
Learn a little about the different types of exception constraints followed-up by a detailed look at the false path, min/max delay and case analysis constraints. We'll also review exception priority and a few tips for constraining exceptions constraints.
This demo design shows SmartFusion®2 SoC FPGA device capabilities for code shadowing from serial peripheral interface (SPI) flash memory to single data rate (SDR) synchronous dynamic random access memory (SDRAM) and executing the code from SDR SDRAM. Code shadowing is a booting method that is used to execute an image from external faster volatile memories (DRAM) and is the process of copying the code from nonvolatile memory to volatile memory for execution. In performance critical applications, execution speed can be improved by code shadowing where code is copied to higher throughput RAM for faster execution.
In this video, Xilinx senior product line manager Joe Mallett shows how a mix of software and dedicated hardware in the Spartan allows an HD signal to be processed in real time, utilizing both VGA and QVGA formats.
See a 2400 Mb/s DDR4 memory interface design running on an UltraScale™ FPGA demonstrate great signal quality and JEDEC compliance as verified by one of Agilent's newest test solutions, the Infinium 90000X-Series oscilloscope.
This white paper explores Altera’s low-power FPGA platform and the video design solutions that address the military’s complex, power-budget-constrained EO/IR design challenges and significantly increase designer productivity. Many of today’s electro-optical/infrared (EO/IR) systems require high-complexity, real-time video processing within a constrained power budget. The latest low-power, low-cost FPGA families are ideal for developing the next generation displa and EO/IR systems.
Allegro PCB Editor timing environment provides a new level of high-speed routing capability to the engineering desktop resulting in up to 60% reduction in route time. Check out the blog post followed by a short video to learn how Timing Vision in action along with AiPT and AiDT make quick qork of a complex DDR interface.
Ever wonder whether the challenges of using partial reconfiguration are worth the benefits? Now, there's an easy-to-use, fine-grain partial reconfiguration methodology that delivers lower cost and power and higher system uptime. What's more, you don't need to understand the intricacies of FPGA architecture to get more usable density from your device.
Prototyping Automation and Debug Software for HAPS FPGA-Based Prototyping Systems Improves Prototyping Performance