Introducing Digitally Enhanced Power Analog

Analog power has always been the standard. New digital power modules offer great flexibility, but that comes with a price. For many applications, we'd love to have the simplicity and efficiency of analog power with the features of digital power. In this episode of Chalk TalkHD Amelia Dalton chats with Steve Stella from Microchip Technology about mixing the best of digital and analog power.

Introducing SDAccel Development Environment

The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

Single-Event Upsets (SEUs) and Medical Devices

Medical devices are not only susceptible to nature’s cosmic rays, but also must operate in radiation environments found in modern medical facilities. As evidence of these effects mounts, designers of medical devices must now also consider SEU susceptibility when choosing the technology that will form the basis for their products. This paper defines what the risks are and explains ways to mitigate and avoid these risks within programmable logic.

Power Reduction in Next-Generation UltraScale Architecture

Designed to scale from 20 nm planar technology through 16 nm FinFET and beyond, Xilinx UltraScale™ devices equip an already-successful architectural platform with numerous innovative power reduction techniques. This white paper explores the challenges of managing power efficiently, reducing device power requirements, and innovating new power solutions at the speed of Moore's law.

AXI4 Interconnect Paves the Way to Plug-and-Play IP

In the past decade, the size and complexity of many FPGA designs exceeds the time and resources available to most design teams, making the use and reuse of Intellectual Property (IP) imperative. However, integrating numerous IP blocks acquired from both internal and external sources can be a daunting challenge that often extends, rather than shortens, design time. As today's designs integrate increasing amounts of functionality, it is vital that designers have access to proven, up-to-date IP from reliable sources.

Leveraging OpenCV and High-Level Synthesis with Vivado

Learn about the OpenCV libraries and typical applications, the advantages of Zynq-7000 AP SoC and implementing OpenCV design, how HLS and video libraries can be used in the process and a demonstration of an example design. For More Vivado Tutorials please visit:

Targeting Zynq Using Vivado IP Integrator

Learn how Vivado® IP Integrator can be used to rapidly configure a Zynq® processor and connect it via AXI4 to a video accelerator running in the programmable fabric of the device. Using built in board aware design rule checks and designer automation, Vivado can greatly improve user productivity.

SDSoc Development Environment Backgrounder

This backgrounder describes the features and benefits of the SDSoC™ Development Environment. The SDSoC development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use an Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment. Complete with the industry’s first C/C++ full-system optimizing compiler, SDSoC delivers system level profiling, automated software acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming. It also enables end user and 3rd party platform developers to rapidly define, integrate, and verify system level solutions and enable their end customers with a customized programming environment.

3D Design and Viewing = STEP Support

With the PCB Editor’s 3D Viewer, the user can see a true 3D graphical view of the PCB. The capability of including enclosures associated with the board is also provided for positioning and collision detection. See how OrCAD PCB Editor makes that possible and allows you to bridge the gap between ECAD and MCAD with STEP model support.

Firm Error Immunity in Flash FPGAs

Radiation effects are not isolated to space electronics only, but they affect all type of electronics whether they are automotive, industrial or military and avionics. What differentiates them is the type of radiation. This webcast shows how FPGA’s interact with them and why Actel FPGAs are the best solution to mitigate these effects.

Virtex-7 2000T FPGA for ASIC Prototyping & Emulation

Watch this video to learn how a complex SoC platform was mapped into a single Virtex®-7 2000T FPGA, the world's largest 3D IC in volume production. With well over 2 million logic cells, the Virtex-7 2000T reduces the need for design partitioning and simplifies the mapping of ASIC RTL. This breakthrough capacity coupled with Xilinx's Next Generation Vivado™ Design Suite provides the ideal solution to tackle the demands of leading edge ASIC and SoC devices.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Leveraging MIPI D-PHY-based Peripherals in Embedded Designs

Embedded systems designers face an ongoing dilemma. On the one hand they need to drive down systems costs. On the other they cannot exploit manufacturing economies of scale because their systems are targeted at relatively narrow, low volume applications. While high volume consumer markets offer components capable of performing similar tasks at much lower cost, embedded designers are restricted from taking advantage of those components by their systems’ reliance on highly specialized, legacy interfaces optimized for the embedded environment.

Improving Performance in Spartan-6 FPGA Designs

Several considerations need to be taken into account to improve the performance of Spartan-6 FPGA designs. This white paper discusses how synthesis and implementation can help to optimize design performance.

Injecting Automation into Verification – Code Coverage

This webinar provides an introduction to the use of code coverage in today’s HDL design and verification flows. Without code coverage the designer will find it hard (or impossible) to know if all aspects of the RTL code have been exercised by the testbench. Code Coverage is built into the simulator and it will tell the designer which areas have been exercised and, much more importantly, which have not.

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