With the advent of low-power CPLDs, low-power electronic product designers now have new options for implementing many of the functions traditionally performed by microcontrollers. This white paper discusses when it is advantageous to use a CPLD instead of a microcontroller, and when it makes sense to use a CPLD as a companion to a microcontroller, with examples grouped into three categories—I/O management, port management, and system management—based on their function and level of complexity.
Transferring High-Speed Data over Long Distances with Combined FPGA and Multichannel Optical Modules
Today’s copper-based high-speed serial interfaces can deliver data at multi-gigabit rates. Data transfer rates exceeding 100 Gbps are possible by using multiple lanes in parallel, but are limited in the distance they can travel. One approach that improves the distance is to use optical interconnects rather than copper. Altera Corporation and Avago Technologies Inc. have jointly developed a solution that combines an FPGA and optical transmitter and receiver modules into a single integrated solution that can replace copper interconnects and multiple card-edge optical transceivers.
Mixed-Signal Power Management: Bridging the Analog-Digital Divide with Mixed-Signal FPGA Graphical Design Configuration Methodology
The management of power at the system level is a challenge faced by all system designers, but designers face a daunting divide between digital and analog when considering tools, practices, and methodologies. A new methodology developed by Actel, implemented in a new design tool, addresses the challenges, and eliminates barriers to delivering user-configurable mixed-signal power management without the need to reprogram circuit design changes to implement configuration changes.
7 series FPGA GTH transceivers have achieved 100% electrical conformance to the 10GBASE-KR standard. In this video you'll see a Virtex®-7 FPGA pass the specification's receiver interference tolerance test over a 24" backplane.
Electric motor efficiency is taking center stage these days not only because the potential power savings are significant, but also because the technology for achieving them is now available. This white paper discusses the factors that are critical in achieving overall system power savings, taking into consideration the rectifier that conditions input power from the AC mains and the variable frequency inverter drive electronics of the motor. Active power factor correction for the rectifier used in modern motor drives is required to keep the generated line harmonics within regulatory limits and reduce wasted power. Mixed-signal FPGAs, by doing many calculations in parallel, can perform better than other possible motor control and power factor correction implementations.
The Intel® Atom™ Processor E6xx Series for the embedded devices market includes the POWERVR* VXE core that provides video encoding capabilities, allowing to encode high definition video streams in the highly compressed H.264 format with a very low main CPU utilization, releasing the general purpose processor for other parallel workloads. This processor feature is available to application developers by means of the open Video Acceleration API (VAAPI ). This paper explains how the VAAPI can be applied to a real time video encoding task, explaining the VAAPI function calls flow, and the corresponding parameters.
In this video, Nick Difiore explains how the capabilities of Xilinx FPGAs allow a switch from mechanical to electronic displays.
The ‘endgame’ for any board design is to generate and manage data from that design for building the physical object captured by that design – and with the utmost integrity. However, the need to ensure high-integrity data often walks hand-in-hand with layers of bureaucratic ‘red tape’, resulting in the designer being confined to design according to formalized processes, locking down design changes to ensure minimal impact to the integrity of the design data.
Watch as we take a look inside the Zynq®-7000 AP SoC ZC706 Evaluation Kit, a transceiver based kit all the necessary hardware, tools and IP to quickly work through your evaluation and development of a transceiver based embedded system. The board gives you access to 16 GTX transceivers running at 6.6 Gb/x on the FMC connector, and the PCIe gen2x4 edge connector fingers.
Liam Madden, Vice President of Silicon Technology takes you through the characterization lab at Xilinx discussing 28nm technology.
IGLOO®2 FPGAs integrate fourth generation flash-based FPGA fabric and high performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable and highest security programmable logic solution. This next generation IGLOO2 architecture offers up to 3.6X gate count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded memory options and math blocks for digital signal processing (DSP)and much, much more.
Advanced FPGAs are difficult to characterized due to their advanced process nodes, which delays the availability of final timing models until silicon characterization is completed. This paper describes the timing models available for end-user FPGA design, in advance of production FPGAs. This paper explains the development cycle of FPGAs, along with the timing models available at each stage. This paper also describes the best practices that you can use at each stage of the timing model.
Altera's 28-nm Cyclone® V and Arria® V SoC FPGAs feature a hard processor system (HPS) containing a microprocessor unit (MPU) with a dual-core ARM® Cortex™-A9 MPCore™ processor, a rich set of peripherals, a multi-port memory controller, and FPGA fabric. The tight integration between the HPS and FPGA fabric supports over 100-Gbps peak bandwidth with integrated data coherency between the processors and the FPGA. The included set of hardened embedded peripherals eliminates the need to implement these functions in programmable logic, leaving more FPGA resources for application-specific custom logic. This combination delivers the flexibility of programmable logic with the power and cost savings of hard IP.
NoC interconnect architectures provide a number of significant advantages over traditional, non-NoC interconnects, such as allowing independent layer design and optimization. Altera's Qsys system integration tool, included with the Quartus® II software, generates a flexible FPGA-optimized NoC implementation automatically, based on the requirements of the application.
PDN designs targeting transceiver (SERDES) FPGAs require clean voltage sources with strict voltage rail requirements. This document describes the advantages of modern switching voltage regulators in a power distribution network (PDN) design to achieve the best FPGA transceiver performance. This white paper provides guidance on voltage regulator selection for low-noise applications, and a test case that demonstrates the transceiver performance for different types of voltage regulators and voltage rail configurations.