Sheep’s Clothing

Can FPGAs Pass as Processors?

by Kevin Morris

For most of the history of FPGAs, the mental model of marketers has been “ASIC replacement,” since FPGAs were designed in the same way as ASICs, and since many applications that would previously have required a custom ASIC could now be done with an FPGA. For many generations, this was the underlying assumption of FPGA evolution - we are trying to replace ASICs.

Every two years - FPGA companies would announce their new families based on the latest process node with great fanfare. “This time,” they would say, “we have devices that truly are ASIC replacements.” Implying, of course, that they had really been ‘just kidding’ all the previous times. And, in fact, each time the statement was a bit closer to the truth. FPGAs, more than just about any other type of semiconductor device, reap direct and powerful benefits from progress in semiconductor technology. With each new process generation, FPGAs made amazing strides - densities doubled, power consumption dropped dramatically, IO bandwidth jumped, clock frequencies ticked up, and the range of applications that could be economically realized grew.

 

Cloudy with a Chance of EDA

FPGAs and Design Automation in the Cloud

by Amelia Dalton

Fish Fry heads into the cloud this week. We talk with two different CEOs from two different EDA companies about how their forays into the cloud set them apart from the rest of the EDA pack and promise to make our design lives a whole lot easier. With Dr. Raik Brinkmann (CEO - OneSpin Solutions) we discuss OneSpin's formal verification tool suite and how it works in the cloud, and why Raik thinks karate and engineering have a lot in common. We also chat with Harn Ng (CEO - Plunify) about how this Singapore-based EDA company is looking to revolutionize the FPGA design process.

 

Weighing UltraScale

Xilinx Announces New Architecture

by Kevin Morris

In the ongoing marketing battle to see who can out-confuse the competition, Xilinx has just fired an impressive salvo. Strapped safely into the cockpit of a superlative-laden press release is an announcement of what the company is calling the “UltraScale” architecture. We would say “new FPGA architecture,” but apparently it isn’t cool to make FPGAs any more. You see, Xilinx is now in the “All Programmable” device business.

Xilinx and archrival Altera have been waging a war of words lately. But, before we whip out the hypesaw and try to slog our way through the formidable layers of marketing bluster and misdirection to find what’s actually cool in this announcement (and hang in there, because there actually is some very high-quality real content buried deep in the core of this fluffball), let’s review the current state of marketing spin in the programmable logic industry:

 

The Artist and the Engineer

by Kevin Morris

My wife is an artist. I am an engineer.

She walks into a room full of abstract paintings and can immediately say, “I like that one and that one and that one - none of the rest.”

I walk into that same room and don’t know what to say. I haven’t got a reason for liking or disliking any of them yet.

Sometime, much later, after analyzing and thinking about them all and worrying that this one has too much orange and that one is overzealous in its use of lucid brush-strokes, I have narrowed my list of favorites down to four. After much additional consideration, I decide to eliminate the first one (although it was my early favorite), leaving me with a final “likes” list of three... the same three she chose immediately, it turns out. Yep, she took about a nanosecond to get the same answer that required my engineering brain a few hours.

 

FinFEUD

Blood Battles in FPGA Marketing

by Kevin Morris

He eyed the horizon suspiciously as he leaned his shotgun against the porch railing and reclined into the wooden seat suspended on chains from the rafters. Things had been a bit too quiet lately, and quiet was never good. Those neighbors of his - he chuckled to himself at the irony of calling them “neighbors,” both because they were several miles apart (although on adjoining properties), and because there hadn’t been a kind word spoken between their clans for the best part of three decades - THOSE neighbors of his were up to something, and he aimed to figure out what it was.

A few miles away, in a musty storm shelter lit by a single incandescent bulb, the neighbors were indeed up to something. They had plans for mister porch swing, and he was not going to like them one bit. They couldn’t wait to see the expression on his face when he realized - far too late - what they’d been building down here. Maybe, finally, this would be their year. The year they settled the score. The year that all that pain and suffering would pay off, and those neighbors would get their comeuppance. It was long overdue.

 

IGLOO2 to You Too

by Amelia Dalton

Fish Fry is headed to the land of programmable logic this week. We're talking FPGA design tools, flash-enhanced FPGAs, and ASIC designs that won't break the bank. We're getting the skinny on Microsemi's new IGLOO2 family from Paul Ekas, chatting about FPGA partitioning with Flexras CEO Hayder Mrbet, and also checking out how Triad Semiconductor can cut your mixed signal ASIC design costs down to a reasonable and career-preserving amount.

 

Building a Bigger Better Igloo

Microsemi Goes Mainstream

by Kevin Morris

Microsemi’s FPGAs - going all the way back to the Actel days - had some interesting and compelling features and advantages. Because their logic fabric was created in flash, they could do certain things that “normal” SRAM-based FPGAs could not. They had very low power consumption, with almost no leakage. They were non-volatile, so you weren’t required to build extra configuration circuitry into your design. They were more immune than others to radiation effects such as single-event-upsets. And, they were comparatively secure - since one could eliminate the vulnerability of bitstream configuration from the final design.

“Wow!” (We would always think). “Those are some great features! But...”

That “but” usually revolved around the fact that Microsemi/Actel’s devices were small. You could take advantage of all those cool capabilities only if your logic needs were extremely modest. If you needed lots of LUTs, you were out of luck.

 

The Next-Node Battle Begins

Altera Announces “Generation 10”

by Kevin Morris

It’s time! Grab your popcorn and settle in for the ride, FPGA fans. The biennial spectacular has just begun. The first gladiator has entered the arena, waved to the crowd, and lifted his weapons. We are about to witness the technological battle of the century in programmable logic.

Every two years, the two big FPGA vendors play a high-stakes game of “chicken” to see who is first to announce their plans for the next semiconductor technology node. At stake - bragging rights for being “first” to announce the next level of capabilities. The risk? Your competitor gets to look at your announcement and use it as a baseline for their own - exploiting any weaknesses in your announced plans and tailoring their own message to stack up favorably. You also risk angering your customers if the announcement precedes the actual product by too much.

 

#50DAC

Technology History Trending in Austin

by Kevin Morris

The 50th annual Design Automation Conference (DAC) in Austin Texas is a landmark event. It is remarkable to think that engineers have been using computer-aided design for electronic systems for more than half a century now. In honor of DAC’s 50th anniversary, there is a small museum in the front of the show with memorabilia (pronounced “swag”) spanning the five-decade history of the conference. Among the T-shirts, coffee mugs, backpacks, and other era-appropriate giveaways, there are photo scrapbooks of years past and samples of conference proceedings. There is even a copy of the proceedings from the very first DAC - “1964 ACM/IEE Design Automation Conference” - held in Atlantic City, NJ June 24-26 1964.

 

Timing is Everything

The Trouble with Timing Closure in FPGA Design

by Kevin Morris

Timing closure is the not-so-fine-print of FPGA design.

PowerPoint presentations paint the process as almost trouble free. FPGA design is simple, right? You just code up some HDL, drop it into the vendor-supplied tool suite, press the magic button - and zzzzzip! Your dev board will spring to life - blinking LEDs and detecting button presses with glee and aplomb. You even try it with the supplied sample code. Yep, sure enough. It’s like microwaving a burrito. Pop off the wrapper, run it through the process, and it’s ready to eat.

Emboldened, you embark on your first “real” design work. This takes some time, of course. You select from a nice assortment of pre-designed IP blocks, stitch them together with the vendor-supplied whizzy-GUI tool, and things are lookin’ good. You run that portion of your design through the tools and - still on track - except for a couple of things you hooked up wrong between blocks, the miracle of field-programmable custom logic is your apple.

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