Plasmons With a Soft GUI Center

RTOS, Nanoelectronics and Scripted Flows

by Amelia Dalton

This week's Fish Fry will not melt in your mouth or in your hand. It will not be crispety, crunchety, or peanut buttery, but it will be coated in EE Journal's signature mixture of electronic design news, in-depth interviews, and nerdy humor. Sweetening the pot, John Carbone (Express Logic) and I dig into some of the evolving trends in embedded software development and baseball franchise loyalty. And finally, fire up your plasmon resonators for a sci-fi trip into the terahertz with the latest nanoelectronic circuit research from the National University of Singapore.

 

Smaller, Cheaper SerDes

Lattice ECP5 Proves Less is More

by Kevin Morris

Over the past few years, Lattice Semiconductor has transformed itself from a struggling, distant third-place supplier of FPGAs to a scrappy, innovative competitor opening up new markets and challenging status-quo perceptions about the nature and role of programmable logic in system designs. Their latest press release proclaims they are “breaking the rules,” which would be easy to dismiss as marketing fluff, but it turns out those big ‘ol marketing boots are walking on some pretty solid footing in this case.

For years, we’ve talked about how FPGAs were trying to “replace ASICs.” In fact, ASIC replacement has been the battle cry of the FPGA companies for about as long as there have been FPGA companies. Every couple of years, with a new family based on a new process node, the FPGA companies come forth and say, “This time, we’ve done it. We’ve made an FPGA that can replace ASICs.”

 

Google's Smartphone Revolution

Inside Project Ara

by Amelia Dalton

A coup d'état is imminent. A mobile revolution. With "Modular!" banners held high and money where their mouths are, Google is marching through the streets determined to overthrow the status quo in smartphone technology. This week’s Fish Fry is all about Google’s Project Ara - why it's cool, why you should care about this modular smartphone technology, and how you can get started designing your OWN modules. My guests are Ara Knaian (NK Labs) and David Rutledge (CTO - Lattice Semiconductor) and we are going to talk about what's inside the Google Ara phone, the important role of FPGAs, and why Ara lent his name to this super cool new project. Also this week, we take a tour of Xilinx’s Vivado IDE and break the biggest news to hit the EE airwaves.

 

Toward Ten TeraFLOPS

Altera Kicks Up Floating Point

by Kevin Morris

The Cray-2, the world’s fastest computer until about 1990, was capable of almost 2 GigaFLOPS (Billion Floating Point Operations per Second) - at an inflation-adjusted price of over $30 million. A decade later, ASCI Red - selling for a cool $70 million or so - topped one teraFLOPS (Trillion Floating Point Operations per Second). The machine was twice as expensive, but the price per performance had dropped from ~$15M/GFLOPS (Cray) to ~$70K/GFLOPS (ASCI Red). That’s a shocking improvement. Moore’s Law would have us believe in a ~32x gain over the course of a decade, but real-world supercomputers delivered over 200x in just ten years. Take that, Dr Moore!

Sometime in 2015, according to Altera, we will have a single FPGA (yep, that’s right, one chip) - designed by Altera and manufactured by Intel - capable of approximately TEN teraFLOPS. Let’s do some math on that, shall we? We don’t know exactly what a Stratix 10 FPGA will cost, but it almost doesn’t matter. This device should put us in the realm of $1/GFLOPS. Or, compared to ASCI Red, an additional 70,000x improvement in cost per performance.

 

Programming QuickLogic’s Sensor Hub

Hardware from a Software Standpoint

by Bryon Moyer

Well, it seems to be sensor hub season. A couple of interesting things are brewing. One, in particular, is of strategic significance, and I’ll be writing that up once I get a chance to dig into some more details.

For today, we’re going to go tactical rather than strategic: we’re going to dig deeper into QuickLogic’s sensor hub solution. And we’re going to get our hands dirty. If you read my earlier piece on sensor hub partitioning, you’ll recall that QuickLogic has a rather intricate implementation that puts much of the sensor hub functionality in FPGA hardware using a combination of low-level software, state machines, and outright hardware. Their claim is that they can achieve the lowest power this way – lower than a more common microcontroller implementation.

 

Heartbleed: Serious Security Vulnerability

Serious Wake-up Call

by Bruce Kleinman, FSVadvisors, foreword by Kevin Morris

Imagine if you woke up one morning, and found out that Walmart was now selling a device for $5 that could easily and instantly open almost any deadbolt lock. That’s right - the kind of lock that is supposed to give “extra protection” to just about every door on earth. That’s the magnitude of security problem posed by the Heartbleed Bug.

Contributing columnist Bruce Kleinman wrote the first half of this article and posted it to his “From Silicon Valley” blog on April 6, 2014. The timing of the post was a remarkable coincidence: just 36 hours before the Heartbleed Bug started making headlines.

As the creators of technology, we engineers need to re-think our commitment to security and safety. The systems we design don’t just earn us money – they are often trusted to protect people’s lives, privacy, and assets. This is a solemn responsibility that is all too often overlooked or given short shrift in our ongoing race to get timing closure, first silicon, working prototypes, and volume shipments.

 

“Softly” Defined Networks

Xilinx Punches Up the Programmability

by Kevin Morris

Programmability is a powerful concept. It allows us to build a physical machine and then modify, upgrade, repurpose, repair, and evolve it - without having to alter the original physical hardware. It allows us to design one device to serve multiple purposes, with variants, upgrades, and value-added features enabled with the flip of a few bits. Programmability extends the life of equipment in the field, reduces inventory requirements, simplifies maintenance and diagnostics, and often eliminates the need to roll a service truck altogether.

In the world of networking, programmability promises these enormous benefits in the extreme. With the global bandwidth glut, network build-out has been a high-stakes, high-priority, big-revenue, full-throttle enterprise for the past three decades - and it shows no signs of letting up anytime soon. If you’re designing network hardware, you already know the drill. You design around the bleeding-edge of what’s possible with current hardware, often against standards that are still in flux, in a race against other companies’ engineering teams that are just as daring and terrified as you are.

 

Exposed by Tools

The Dark Side of Reporting Features

by Bryon Moyer

Do you like to be watched while you work?

Most people don’t. There’s this fine line between making sure that stakeholders know about your progress on a project and having those stakeholders all up in your business all the time. The latter is micromanagement, and no one likes that.

More and more EDA tools are being provisioned with management and reporting features. These make it easier for you as a designer to let your supervisor or project manager know what you’ve accomplished and what remains – and you spend less time writing up those annoying status reports.

 

Augmented Reality

A Compelling Mobile Embedded Vision Opportunity

by Tom Wilson, Brian Dipert, Marco Jacobs, Tim Droz

The prior article in this series, "Embedded Vision on Mobile Devices: Opportunities and Challenges," introduced various embedded vision applications that could be implemented on smartphones, tablet computers and other mobile electronics systems (Reference 1). In this and future articles, we'll delve into greater implementation detail on each of the previously discussed applications. Specifically, this article will examine the processing requirements for vision-based tracking in AR (augmented reality), along with the ability of mobile platforms to address these requirements. Future planned articles in the series will explore face recognition, gesture interfaces and other applications.

Computer graphics pioneer Ivan Sutherland established the basic concepts of AR as known today in his seminal 1968 paper “A Head-Mounted Three Dimensional Display” (Reference 2). Sutherland wrote, “The fundamental idea is to present the user with a perspective image which changes as he moves.

 

Board Revolution

Part 2 - Mentor Xpedition

by Kevin Morris

Mentor Graphics is number one in PCB design tools. They want me to tell you that. They want me to tell you that - even after reading about my disdain for marketing the market share of your product. So - there ya go. They’re number one. Why does this matter? Well, they rightfully point out that nobody ever got fired for buying the leading tool, and that EDA can be a fickle business. If an EDA tool is number one (they observe), the company selling it probably cares about it deeply and will want to go the distance to support you and make you happy. Point taken.

However, since we’re all engineers here, the thing that matters the most - by FAR - is whether the tool is robust and reliable in helping you get your engineering job done. In this case - that means helping you be as productive as possible designing the heck out of your PCB. Luckily, besides being number one, Mentor has done a very respectable job of that as well. Now, however, they think that’s not enough. They’re launching a big ’ol ambitious program to upgrade their PCB design suite - in a clear effort to fend off the similarly ambitious competitors (Cadence, Zuken, Altium, et al) who are coming full-tilt right at them.

subscribe to our fpga newsletter


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register