Overvoltage Protection in High Speed Communication Ports

by Ian Doyle, ProTek Devices

Editor's Note: While Amelia's Halloween Fish Fry had us all running out and gleefully building our own singing Tesla coils, and even though shuffling quietly across the carpet and sending a bright 10,000-volt arc from your fingertip to a napping family member can be a barrel of laughs, there are times where we most definitely do not find electrostatic discharge so amusing. The first of those, of course, is when we ARE the sleeping family member. Sheesh, what an insensitive prank!

But, a second scenario where we do not welcome the effect of high-voltage static discharge events is when we're designing high-speed communications circuits. Getting your Ethernet port zapped with a 10kV ESD is far from fun - especially for the Ethernet port. But, how do we help our circuits protect themselves? Ian Doyle of ProTek devices has some very helpful suggestions.

--Kevin Morris, Editor-in-Chief

Transmission data rates continue to grow and grow to meet consumer demands for multimedia rich content, such as streaming video. In turn, whether in the home or at the backend, Ethernet connectivity also continues its widespread use. As a result, and more than ever, electrostatic discharge (ESD) transient threats pose challenges to system designers to incorporate overvoltage protection that doesn’t impact performance.


Sights on Systems

Mentor Elevates PCB Game

by Kevin Morris

For decades, the PCB design tools competition has been a board game. The scope of the problem was the design of a single PCB, and the competitors - Mentor, Cadence, Zuken, Altium/Protel, and the rest - all battled for supremacy with the scope, features, power, and cost of their solutions. The market for board tools actually got a little boring for years, with the major players competing mainly on cost and incumbency in the high-end (enterprise) level and in the low-cost (desktop) markets.

In the past few years, however, the battle has been heating up again. Demands on even “ordinary” board design have grown, as signal- and power-integrity became common problems with higher speed components, and IC packaging and mounting technology caused new challenges for layout. As a result, “desktop” tools began to inherit many of the features associated with “enterprise” tools. Enterprise design tool suites had to once again scramble to differentiate themselves and justify their significantly higher costs.


Moore’s Law Meets the Trade Press

EE Journal Turns 11

by Kevin Morris

We live and work in an amazing time. The global community of electronic engineers has created the greatest leap of technological progress in human history. In the almost fifty years that Moore's Law has existed, the number of transistors we can put on a single chip has risen from fifty to somewhere around twenty billion. That is a truly amazing achievement. And the power of that almost unimaginable feat has rippled and ripped through just about every aspect of our lives and our culture.

As the creators of that change, we have faced a unique challenge. While the rest of the world gets to enjoy the fact that electronic technology doubles in capability every two years, electronic engineers are faced with the harsh reality that we have to double our own productivity on that same schedule. Moore's Law becomes our mandate. I am aware of no other profession that requires a constant exponential improvement in worker productivity just to stay in the game.


New Chips are HIPP

A Modest Proposal for a New Name

by Kevin Morris

It’s time to speak up for the silent, to give a voice to the voiceless, to defend the downtrodden. Today is the day for action - for the engineering community to unite and right a wrong. We need to come to the aid of a technology in need, to give a name to the nameless. History is watching and will judge us by how we handle this epic dilemma.

I was giving a talk at an FPGA-related technology event recently, and the discussions in the room turned to the new category of devices that combine conventional processors with FPGA fabric on the same chip (or in the same package). These devices, like Xilinx Zynq, Altera SoC FPGAs, and others truly represent a new category of chips. While putting an FPGA next to a conventional processor is nothing new, there are major advantages to combining them into a single device that brings compelling new capabilities to the table.


Tabula Tames Verification

DesignInsight Brings Unique Debugging Superpowers

by Kevin Morris

I have to prepare myself any time I go to meet with Steve Teig from Tabula. Steve is a bona-fide genius, and any time I talk with him I feel like I have to have my mental running shoes tightly laced. Steve brings a level of creativity and insight to the table that one seldom encounters, and when he’s telling you about a new thing, you can bet it will be something you didn’t expect.

So, when I went to Tabula for a briefing with Steve on what has now been announced as the new DesignInsight technology, I knew it wouldn’t just be another one of your typical hum-drum, “we added a completely predictable new feature to our chips” kinda deal. I wasn’t disappointed.

Tabula, for those of you who haven’t been following along, makes programmable logic chips that are probably most closely related to FPGAs. They are similar in that they feature an array of logic cells based on look-up-tables (LUTs) that can be programmed and interconnected to perform a variety of logic functions.


Max 10 Kills the CPLD

Altera Redefines Non-volatile FPGAs

by Kevin Morris

The venerable CPLD (Complex Programmable Logic Device), forefather of today’s flourishing FPGA and programmable logic industry, died peacefully in its sleep last night of natural causes. No memorial services are planned. The CPLD is survived by an incredible array of modern, capable devices that take the concept of programmable hardware to places never envisioned by the stately senior sum-of-products statesman.

If you visit the Wikipedia page for “CPLD” you will find a picture of an Altera MAX device (EPM7128), a 2,500 gate-equivalent, 128 macrocell “second generation” CPLD (or “EPLD” as the company was spinning it in those days) which, according to the datasheet, was capable of implementing “complete system-level designs.” That is, of course, if you were designing a “system” that could be implemented in well under 2,500 gates, was all digital, and had a 2-digit number of IOs.


Expanding EDA

Newer Tools Let You Do More than Just Electronics

by Bryon Moyer

Welcome to autumn. It’s usually a busy season – although the activity typically starts more with the onset of September and the resumption of school than with the equinox. But it also comes on the heels of a quiet season, even in the overworked US.

And EDA has seemed moderately quiet. So I started looking around to see what I might have been missing, and I’m not sure there’s a lot. But it did get me musing on why things might be quiet for the moment as well as what fills the gap – which gets to the topic of what qualifies as EDA. It’s more than you might think.

At the risk of being obviously over-simple, the legions of coders in EDA-land are doing one of two things: building new technologies or improving on old ones. The new technology category might include support for FinFETs or multi-patterning or the design kits for the latest silicon node. The improvement side of the tree is where performance and capacity and usability are juiced up – all in the name of productivity, of course.


The Four Horsemen

What Does the Future Hold for the Semiconductor Industry?

by Dick Selwood

When I looked at the forecasts from London-based analysis company Future Horizons this time last year (Malcolmy: Entrails, Crystal Balls and Spreadsheets), I saw that they predicted that, while short-term (through 2014) sales volumes were set to increase, the long-term future of the industry was looking a little less than rosy. A year on, the picture Malcolm Penn, the MD of Future Horizons, is painting is much the same, with the pessimism for the long term even more marked.

First - the good news: Penn has revised upwards his forecast for the number of ICs shipping. His downside forecast shows growth of 9.8% and his upside predicts growth of 11.2%. For 2015 he is going for 15% growth, perhaps more.


Makers Conquer the World

From Artisan to Arduino at World Maker Faire

by Kevin Morris

We walk past a small booth at the 2014 World Maker Faire, and a young boy, perhaps eight or nine years old, jumps out to get our attention. He is so excited we can barely understand what he is saying. He wants us to see his sneakers - adorned with an array of LEDs giving a high-energy light show that would make any grade-schooler envious. He explains that he programmed the lights himself. He is ecstatic, and his enthusiasm radiates into the crowd. “Can I sign you up? Can I sign you up?” He pulls up a registration form on a laptop computer. We have no idea what he wants us to sign up for.

A look inside the sneakers reveals an Arduino board with its obligatory Atmel AVR microcontroller. Sitting on the table nearby is another laptop - running a kid-friendly drag-and-drop programming interface that allows kids to write code to create their own shoe-wear lighting spectacular. You want blinky shoes? You gotta program them first. It’s gonna be FUN!


Go-Fast FPGA Design

Helpful Hot-Rodding Hints

by Kevin Morris

Most of us engineers are at least closet hot-rodders. It’s in our DNA. No matter how good a contraption is from the factory, we just can’t resist the temptation to tweak a few things in our own special way, and often that’s all about speed.

FPGA design, it turns out, is a big ‘ol blank canvas for hot-rodding. Even though we (fortunately) don’t have glossy convenience-store magazines adorned with scantily-clad models standing next to the latest tricked-out dev boards, FPGAs have all the tools we need to rev our creative motors in the never-ending quest for that extra little bit of personalized performance.

But, where do we start? Do FPGAs have a set of go-to hop-ups? Is there a “chopping and channeling” baseline for programmable logic design?

It turns out the answer is “yes.” And, just to get you started, here are five tips for turning up the boost on your next project:

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