Tools! Tools! Tools!

Debuggers and Boards and IDEs! Oh, My!

by Jim Turley

If this is February it must be Nürnberg. Or Barcelona. Either way, it’s the month when embedded developers head to Central Europe. (The ones with travel budgets, anyway.) And it’s the month when embedded vendors roll out their latest toys. It’s like attending Milan Fashion Week or the Paris Auto Show except… you know… less glamorous.

Two of my favorite announcements this week came from smallish companies, and both have been in the business for a while. And both have to do with tools. Software-development tools. The things that make the embedded world go ’round.

 

Xilinx Throws Down

Unveils New 16nm UltraScale+ Families

by Kevin Morris

When the #1 FPGA company makes what is arguably their biggest new-technology announcement in a decade, you’d expect there to be a lot of substance. With this week’s announcement of UltraScale+ Virtex, Kintex, and Zynq devices planned to roll out on TSMC’s 16nm FinFET process, the company did not disappoint. This is one of the broadest, most complex announcements we have ever heard from Xilinx. So, with that preface, let’s take a look at what those folks on the south side of San Jose have been up to lately.

In summary, Xilinx is announcing new Virtex, Kintex, and Zynq families of programmable devices with major improvements in capability over previous generations.

 

Soup to Nuts

Design Verification’s Party of the Year and Supply Chain Risks We Should Avoid

by Amelia Dalton

In this week’s Fish Fry, we’re serving up a virtual smorgasbord of EE goodness! First up, it’s a trip to the global supply chain salad bar with Lynn Torrel from Avnet. Lynn and I dig into the biggest trends driving the global supply chain, the challenges of multi-dimensional supply chain security, and which supply chain risks you should take head on. Our next guest is Yantin Trivedi who’s here to spill the beans on this year’s biggest design verification party - DVCon 2015. Finally, we round out our scrumptious EE feast with a look into how we can banish the ugly mixed-signal verification monster once and for all.

 

Achronix Beats the Odds

Full Production on High-Performance FPGAs and Tools

by Kevin Morris

Few challenges in the world of high-technology startups are as daunting as that of putting a new FPGA company on the map. Sure, there’s the obvious hurdle of coming up with a better mousetrap - against two extremely innovative and experienced mousetrap makers who most certainly have deeper pockets than you. And deep pockets matter. If you don’t have the resources to deal with the nine-digit-dollar entry fee for new device development at competitive process nodes, you’re better off not leaving the starting line.

Then, there’s the matter of timing the waves. Let’s say you came up with a fancy new FPGA design, and you planned to implement it at 28nm. If you started designing at about the time 28nm technology was first available, and you executed your design project perfectly, you’d at least be on an even playing field with the big established companies. (Not that the even playing field would help that much, given that the other teams have about 50x the number of players you’re fielding.) But chances are, you didn’t execute your design project perfectly, and chances are, the semiconductor fab didn’t give you top priority compared with their long-time high-paying partners. That means you launched your 28nm a year or so later than the big guys.

 

Engineering Childhood’s End

Radio Shack Goes From 50-in-1 to None

by Kevin Morris

My fingers trembled and my heart pounded. I carefully bent spring terminal #35 and inserted the tinned end of the final wire. I was confident that I had double-checked every connection, but I still felt unsure.

Nothing happened.

As I slowly turned the knob labeled “variable condenser,” I thought I heard a hiss or some static. Then, suddenly, Merle Haggard singing “Branded Man” boomed through my tiny earphone. I jumped! I couldn’t believe what I was hearing. I hated country music, and it was the most beautiful sound my seven-year-old ears had ever heard.

 

Tabula Nada

Innovative FPGA Company Calls it Quits After 12 Years

by Jim Turley

Call it aggressive; call it innovative; call it bat-poop crazy. Whatever your views, Tabula certainly had interesting ideas about how to design an FPGA. But now it’s gone.

The Santa Clara–based startup will close its doors at the end of next month. The staff have all been given their walking papers. The furniture and fittings will presumably go up for auction, a common-enough sight here in Silicon Valley. And the technology? Tabula’s secret sauce may wind up in the hands of an investor, or a new startup, or some big established semiconductor vendor, or a patent troll. Too early to tell.

 

When Smaller is Better

Lattice Introduces iCE40 UltraLite

by Kevin Morris

There has been a lot of chest-beating over the years about who had the biggest, fastest FPGA in all the land. Countless press releases, PowerPoints, and posters have touted 30% better this and 4x more that. Each time a competitor leapfrogged the other, we lapped up the LUTs with renewed glee.

Lately, however, Lattice has been pushing the other end of the envelope, proudly proclaiming that they make the very smallest FPGAs. These FPGAs are so small, power-efficient, and cheap that they completely rewrite our notion of FPGAs. Literally everything you probably thought you knew about FPGAs is busted by these devices. Ask the average engineer and you’ll probably hear that FPGAs are big, expensive, power-hungry, and useful mostly for prototyping. They’ll generally continue that FPGAs would not work in mobile or battery-powered devices, aren’t useful for space-constrained designs, and would never-ever be found in a smartphone teardown.

 

MathWorks Targets Hardware/Software

Prototyping MATLAB and Simulink Algorithms on Xilinx Zynq and Altera SoCs

by Eric Cigan, FPGA/SoC Technical Marketing, MathWorks

The year 2011 saw a signature development in the FPGA industry – the introduction of two new programmable SoC devices. Xilinx introduced the Zynq-7000 All Programmable SoCs, and Altera introduced the Cyclone V SoC and Arria V SoC FPGAs. These new programmable SoCs, each packing a high-performance dual-core ARM Cortex-A9 MPcore along with ample amounts of programmable logic, offered advantages for a plethora of applications. Now designers could enjoy the benefits of software application development on one of the industry’s most popular processors while gaining the flexibility and throughput potential from hardware acceleration on a high-speed, programmable logic fabric.

 

Verifying Your Awesomeness

The Mire of Modern System Verification

by Kevin Morris

If a clock tree fails in a forest, and there are no vectors to catch it…

Verification has always been the black sheep of the engineering family, and for understandable reasons. Design teams are made up of intelligent, capable, and - dare we say occasionally arrogant - types who don’t take kindly to the notion that their work contains errors. Yet, we have verification teams who make their entire career finding the bugs in the work of designers.

Does this sound like a recipe for peace and harmony?

As system complexity has exploded, design productivity has largely kept pace. There is, of course, the ubiquitous EDA marketing slide - a graph over time showing an expanding “gap” between the number of gates we can design and the number of gates Moore’s Law will allow us to put on a chip.

 

Silicon Fingerprints and Smartphone Modules

Adventures in Unclonable Function Technology and Project Ara Development

by Amelia Dalton

Ready. Set. Authenticate. This week’s Fish Fry investigates how Microsemi FPGAs are changing the cyber-security landscape one PUF (Physically Unclonable Function) at a time. My guest is Tim Morin from Microsemi. Tim joins Fish Fry for the first time - discussing the zeros and ones of PUF technology, explaining why it's so important to today’s IoT products, and revealing what it's really like to own fourteen (whoa) horses. Also this week, I unveil some seriously cool news from the most recent Google Project Ara Developer’s Conference.

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