Building a Bigger Better Igloo

Microsemi Goes Mainstream

by Kevin Morris

Microsemi’s FPGAs - going all the way back to the Actel days - had some interesting and compelling features and advantages. Because their logic fabric was created in flash, they could do certain things that “normal” SRAM-based FPGAs could not. They had very low power consumption, with almost no leakage. They were non-volatile, so you weren’t required to build extra configuration circuitry into your design. They were more immune than others to radiation effects such as single-event-upsets. And, they were comparatively secure - since one could eliminate the vulnerability of bitstream configuration from the final design.

“Wow!” (We would always think). “Those are some great features! But...”

That “but” usually revolved around the fact that Microsemi/Actel’s devices were small. You could take advantage of all those cool capabilities only if your logic needs were extremely modest. If you needed lots of LUTs, you were out of luck.

 

The Next-Node Battle Begins

Altera Announces “Generation 10”

by Kevin Morris

It’s time! Grab your popcorn and settle in for the ride, FPGA fans. The biennial spectacular has just begun. The first gladiator has entered the arena, waved to the crowd, and lifted his weapons. We are about to witness the technological battle of the century in programmable logic.

Every two years, the two big FPGA vendors play a high-stakes game of “chicken” to see who is first to announce their plans for the next semiconductor technology node. At stake - bragging rights for being “first” to announce the next level of capabilities. The risk? Your competitor gets to look at your announcement and use it as a baseline for their own - exploiting any weaknesses in your announced plans and tailoring their own message to stack up favorably. You also risk angering your customers if the announcement precedes the actual product by too much.

 

#50DAC

Technology History Trending in Austin

by Kevin Morris

The 50th annual Design Automation Conference (DAC) in Austin Texas is a landmark event. It is remarkable to think that engineers have been using computer-aided design for electronic systems for more than half a century now. In honor of DAC’s 50th anniversary, there is a small museum in the front of the show with memorabilia (pronounced “swag”) spanning the five-decade history of the conference. Among the T-shirts, coffee mugs, backpacks, and other era-appropriate giveaways, there are photo scrapbooks of years past and samples of conference proceedings. There is even a copy of the proceedings from the very first DAC - “1964 ACM/IEE Design Automation Conference” - held in Atlantic City, NJ June 24-26 1964.

 

Timing is Everything

The Trouble with Timing Closure in FPGA Design

by Kevin Morris

Timing closure is the not-so-fine-print of FPGA design.

PowerPoint presentations paint the process as almost trouble free. FPGA design is simple, right? You just code up some HDL, drop it into the vendor-supplied tool suite, press the magic button - and zzzzzip! Your dev board will spring to life - blinking LEDs and detecting button presses with glee and aplomb. You even try it with the supplied sample code. Yep, sure enough. It’s like microwaving a burrito. Pop off the wrapper, run it through the process, and it’s ready to eat.

Emboldened, you embark on your first “real” design work. This takes some time, of course. You select from a nice assortment of pre-designed IP blocks, stitch them together with the vendor-supplied whizzy-GUI tool, and things are lookin’ good. You run that portion of your design through the tools and - still on track - except for a couple of things you hooked up wrong between blocks, the miracle of field-programmable custom logic is your apple.

 

Learning Ability

Superpowers for Engineers of the Future

by Kevin Morris

When we choose engineering as a career, we are making a decision to become lifelong students. The crazy pace of technological change means that we must be constantly learning and re-learning our art. The day we stand still and stop checking our assumptions against the latest developments is the day we begin to become irrelevant as engineering professionals.

During the past two decades, however, an amazing shift has occurred. Because of the information revolution, learning itself has changed. In addition to learning new stuff about engineering and technology, we actually have to re-learn how to learn.

If learning about a new technology is like developing a new software application, re-forming our learning process is like developing a new operating system. Fundamental assumptions about how we obtain, evaluate, and retain information have to be thrown out and re-formed.

 

ASIC is a Four Letter Word, Napalm Bats, and The GertBoard

by Amelia Dalton

Fish Fry is treading on scary ground this week. Guard your children, hold your RTL close and your soldering gun even closer. We're talking ASIC design costs. I know many of you are cowering in fear at the slight mention of custom chip NRE costs, but my guest is Reid Wender (Triad Semiconductor) and we're chatting about how you can relinquish your mixed-signal ASIC design cost fears once and for all. Think of it as an NRE exorcism, sorta.

 

Finding Your Power Animal

Altera Acquires Enpirion

by Kevin Morris

OK, FPGA designers, are you sitting down? We need to visualize. Relax. Close your eyes. Breathe in, breathe out, go to your calm and happy place. Everything is going to be OK. You are floating on a warm pond. Your FPGA design is working on the dev board. You feel the sun on your face. You are strong and confident...

Now, we will begin. You are going to design the power supply for your high-end FPGA. It is going to go smooooooothly. There will be no mess of passive components interacting in weird and unexpected ways. You won’t have to call in the guys from the next building who wear the tie dye and sandals to work. Your design will not misbehave in strange and inexplicable ways that are later discovered to be the result of slightly-out-of-spec power.

 

TECHURMUDGEON

You Kids Get Off My LAN!

by Kevin Morris

The command line interface is where real work gets done. If he touches the mouse too many times during the day, he starts to feel like a sellout. GUIs are for wussies. He’s used vi exclusively for editing since 1980, and he thinks the whole concept of WSIWYG is a sham. Social Media? What’s that!? He is - The Techurmudgeon.

They say that most people listen to new music only until they reach age 21. After that, they keep listening to the same music they loved during the 16-21 years - over and over again for the rest of their life. Apparently, the theory goes, those “coming of age” years are tightly connected with people’s musical sensibilities. The songs of our youth become the songs of our lives.

 

Ultra-Low Power Strikes Again

by Amelia Dalton

Show me an engineer that isn't worried about power consumption and I'll show you a bridge I'd love to sell you. Getting the power consumption down in your designs can be a tricky dance. From the semiconductor process, to the components you choose, to the embedded software you use, just about every decision you make affects your system power. In this episode of Fish Fry, we're talking to Gordon Hands (Director of Marketing - Lattice Semiconductor). Gordon and I chat about the world's smallest FPGAs and what ultra-low power devices can do. Also this week, I'm talking with Alf Bogen (CMO - Energy Micro) about how Energy Micro is making a name for themselves in the low power business.

 

Mobile Drives Everything

The Quiet Shift in Semiconductor Conductors

by Kevin Morris

Nice job folks! Over the past few decades, we electronic engineers have created social change so dramatic that previous discontinuities like the Renaissance, the Industrial Revolution, and two world wars pale in comparison. Nothing in human history can rival the technological progress that has been achieved in electronics and the impact of that progress on civilized life.

We go to work each day, month, and year - and our baseline assumption is exponential improvement. Think about that a minute. We’ve all taken math (lots of it, in this profession). Exponentials in the real world are never sustainable. Yet, we work away in our jobs expecting the number of transistors on a chip to double every two years, just as sure as we expect the sun to rise in the morning. Biennial doubling of capability is reduced to status quo.

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