Flex Logix Debuts FPGA Cores for IC Designers
Kato, Robin, Watson, Tonto, Spock, Barney, Hutch, Higgins, FPGAs - everyone knows the importance of a top-notch sidekick. We’ve seen FPGAs teamed up with countless heroes, parked next to just about every type of device you can imagine. And FPGAs are steadfast in the fulfillment of their duties - bridging the logic, driving the interfaces, accelerating the processing, scaling the video, integrating the peripherals - no task is too unglamorous for the hard-working FPGA - and it often manages several of these at once.
Today, if you’re designing a custom chip, chances are you’ve already considered putting an FPGA next to it. And that’s before your custom design is even done. There are just too many variables in a new design, and you have to assume that you won’t have them all nailed down before you tape out. There may be some standards that aren’t solidified yet (and you certainly don’t want to wait for standards committees to finish their seemingly-endless deliberation before you proceed with your design).
Molex and the Connectors of Tomorrow
They’re super important, and every design needs them, but let’s face it - connectors have gotten a bad rap for being a bit boring. In this week’s Fish Fry, we explore into the multi-faceted world of today’s connectors and cables where signal integrity rules the roost and multi-gigbit SerDes is king. My guest is Joe Dambach (Molex) and we discuss how Molex is using correlated models to solve today’s signal integrity and high-speed serial design challenges, how datacenters are changing the face of connector and cable technology, and why connectors and cables aren’t as boring as we once thought they were. Also this week, we look into this week’s hottest rumor swirling around the EE halls: Will Intel buy Altera?
Deterministic Processor an Alternative to Typical Code Drivers
Oftentimes, the decision comes down to “FPGA or ASIC.” But what if the decision was “FPGA or microprocessor?”
That’s essentially the value proposition from XMOS, the British microprocessor company that pitches its products not as alternatives to the usual rogues’ gallery of CPUs, but as an alternative to an FPGA.
And now that decision gets a little bit tougher.
You see, in the usual hardware/software partitioning that we’re all familiar with, you start out with fixed hardware resources (some combination of a CPU or MCU, some fixed logic, and maybe some programmable logic) and then you begin to apply software. Pretty standard, right?
What Would it Mean?
There has been rampant speculation this week on rumors that Intel is in negotiations to buy Altera - in a deal that should be worth over ten billion, and which would be the largest acquisition in Intel’s history. While neither company is saying anything public yet, there is a substantial amount of information available from which to evaluate the potential impact of such a move and to speculate about the reasons behind it.
We actually predicted this eight months ago in our aptly-named article “When Intel Buys Altera” (subtle title, no?), and the arguments we made back then still apply today. But, with almost another year of progress under our collective belts, we should be able to raise the resolution on our crystal ball considerably. While there has been a considerable amount of press and analyst attention on these rumors, we think the analysts are largely off base. We’ll go into the problems with the analyst theories separately, but, for now, here is our take:
Also - please note that there has not been any deal announced as of this writing. We are speculating here - caveat emptor.
Cadence Stratus Ushers In a New Era
It’s been more than twenty years since I started working on high-level synthesis (HLS). You might say I’ve studied the topic a lot. For most of those two-plus decades, HLS has been widely considered the “design methodology of the future.” And there are those who have held onto the belief that it always will be.
For those of you not in tune with the terms, high-level synthesis is the automatic creation of hardware architectures from behavioral descriptions. At first, HLS was known as “behavioral synthesis.” But, after some early bad experiences, the EDA industry quietly shifted the name over to HLS - hoping that nobody would notice or have episodes of PTSD when confronted with the idea.
Xilinx Announces SDSoC
The world of system design used to be a simple place. Hardware engineers designed hardware, and software engineers wrote software. The hardware folks sat in labs, hooked things up with wires and connectors and soldering irons, and worried about current and voltage. The software engineers sat in front of computers, used editors and debuggers, and wrote, worried about, and debugged code. They played on different company softball teams, ate in different parts of the company cafeteria, and wore different styles of clothing.
Then, one day, hardware started to become a little more like software. Hardware engineers found themselves sitting in front of computers a lot of the day - writing and debugging HDL code - and then running into their labs to resume their work with scopes and soldering irons. If they were designing with FPGAs, they became even more like software engineers. It didn’t seem like a huge change, but it was the first step toward where we are today.
The Next Big Thing?
The scene: A hotel breakfast room. There are several groups, mostly of men wearing the same logo-marked polo shirt, or matching ties, speaking English and having breakfast. Out of one group comes, "Their BIOS was rubbish, so we had to write a completely new one." Welcome to Nuremberg during embedded world.
For three days all the hotels are packed, despite having doubled their room rates. The U-Bahn (Metro) adds extra services from the city centre to the Exhibition site, and over 900 exhibitors are visited by more than 20,000 people. Amongst them are the editors, rushing around to their long list of press conferences and press briefings. During three days I spoke to around 4% of the exhibitors in formal meetings and a few more in informal sessions. I also received many, many press releases associated with products being launched at the show. (As I write, my inbox is being flooded with Mobile World Congress releases - in fact, so many, they are even overtaking the spam.) What follows is my attempt to capture the main trends in embedded systems based on those meetings and on the way in which companies were branding their booths.
Who Does What and With What?
For years now various people have been tracking the EDA process for ASICs and SoCs, and we have a pretty good idea of what the problems are and where the bottlenecks are. (Although we don't seem, for some reason, to be able to take corrective action to solve the problems and remove, or at the least, ease the bottlenecks.)
FPGAs are now generally big beasts, comparable in complexity to the custom products of only a few years ago. To some extent, their development process has not been tracked, in part because (usually) the developers use the tool chain supplied by the FPGA company, and so there is less commercial interest in the big EDA companies who are not making much of a mark in this area. Management loves free tools, although, as the FPGA companies spend a lot of money on developing and maintaining these tools, in the cost of each chip there is a significant chunk covering the cost of the software.
Putting Your Tools Where Your Mouth Is
Breaking into any part of the FPGA market ecosystem is a substantial challenge. Countless companies have launched with various novel ways to take advantage of FPGA technology, and the countryside is littered with the carnage of their decaying carcasses. It’s not a friendly environment out there in FPGA land.
Ironically, the biggest danger for FPGA startups is the FPGA companies themselves. Their track records over the past couple of decades have established them as shining examples of the “frenemy” concept. In order to succeed in FPGAs, you have to partner with the FPGA companies. Then, at some point, you generally find yourself competing with them in one way or another - usually by trying to sell tools or IP that they give away for free.
Achronix Takes Speedster to Production Prime Time
The green flag dropped long ago. The pole-sitters have put the pedal to the metal on their high-octane beasts and vanished around the bend. Circling the course, the leaders of the pack fly ahead, their eyes fixed on the twists and turns of smaller and smaller geometries, without even a glance into the rearview. Don't look now! A dark horse is coming up quickly and quietly, stealthily stalking both leaders, attacking their most profitable lines. The programmable logic race has been ruled by a duopoly for years, but now an up-an-comer looks to change the race - once and for all. My guest this week is Robert Blake (CEO - Achronix) and Robert is here to discuss how Achronix is speeding ahead to full volume production, why (sometimes) it's best to buy and not invent new parts for their FPGA engine, and what it's like to be a pilot in the Bay Area.