Collision of Two Worlds

The FPGA Supercomputing Nexus of Hardware and Software

by Kevin Morris

We are always trying to make machines that think faster. Before we finish building computers that can solve the last generation of problems, our imagination expands and we have a whole new set of challenges that require a new level of computing power. Emerging applications like machine vision can seemingly consume all of the computing power we could possibly throw at them - and then some.

For the past couple of decades, a quiet but radical minority has seen FPGAs as a magic bullet in the quest for more computing power. However, the challenges of programming FPGAs for software-like tasks was daunting, and the inertial progress of von Neumann machines surfing the seemingly-eternal wave of Moore’s Law was sufficient to keep our appetites sated.

However, the monolithic von Neumann machine ran out of steam a few years ago.

 

Dawn of a new Ara

What’s Google’s New Modular Smartphone Really About?

by Kevin Morris

It would be easy to blow off Google’s “Project Ara” modular smartphone concept as just another one of those Google science fair projects that will never come to anything. Remember “Google Wave” anyone? Yeah, we were all “waving” bye-bye to that one before it ever got off the ground. As engineers, we all know that only one out of every dozen or more cool technology ideas ever comes to anything interesting. But, Google’s propensity for over-funding lots of blue-sky projects just to see if anything sticks is well known, and it is a fertile breeding ground for highly-public failures.

The marketing for Ara doesn’t help much either. Billed as the “smartphone for the next five billion people,” the marketing concept just doesn’t hold water. The implication is that all those people out there who currently don’t have a smartphone (you know the ones) have been just waiting around patiently until somebody gave them a phone they could customize with various application processors, wireless modules, memories, screens, cameras, and accelerometers. Hmmm… Just take a quick poll of the folks you know who don’t yet have a smartphone. Think it’s because they really really want the quad-core? Yeah, me neither.

 

Viva Vivado!

Xilinx Tunes-Up Tools

by Kevin Morris

As we enter what will perhaps become the “long tail” of Moore’s Law, the traditional battlefield for FPGA companies is shifting dramatically. For most of the history of FPGAs, the main strategic goal was to be “first” on each new process node. If you had FPGAs ready to go on the newest, fastest, densest semiconductor process, you had a significant advantage over your competitor. With each new node, the cost dropped, the power efficiency improved, performance took a leap ahead, and functional density doubled. The combination of those advantages was so substantial that almost nothing your competitor could do would offset a one-node advantage.

Today, however, those new nodes are much harder fought, and the rewards are much more modest. No longer are PPC (performance, power, and cost) automatic “wins” just from moving to the new technology. Leakage current, skyrocketing NRE and mask costs, complex design constraints, and other challenges have forced FPGA companies to make hard compromises among these critical components of semiconductor goodness. Both Xilinx and Altera now have split lines - where “current” devices are not all made on the same process node, and differentiating FPGA product offerings based on process alone has become a losing proposition.

 

Plasmons With a Soft GUI Center

RTOS, Nanoelectronics and Scripted Flows

by Amelia Dalton

This week's Fish Fry will not melt in your mouth or in your hand. It will not be crispety, crunchety, or peanut buttery, but it will be coated in EE Journal's signature mixture of electronic design news, in-depth interviews, and nerdy humor. Sweetening the pot, John Carbone (Express Logic) and I dig into some of the evolving trends in embedded software development and baseball franchise loyalty. And finally, fire up your plasmon resonators for a sci-fi trip into the terahertz with the latest nanoelectronic circuit research from the National University of Singapore.

 

Smaller, Cheaper SerDes

Lattice ECP5 Proves Less is More

by Kevin Morris

Over the past few years, Lattice Semiconductor has transformed itself from a struggling, distant third-place supplier of FPGAs to a scrappy, innovative competitor opening up new markets and challenging status-quo perceptions about the nature and role of programmable logic in system designs. Their latest press release proclaims they are “breaking the rules,” which would be easy to dismiss as marketing fluff, but it turns out those big ‘ol marketing boots are walking on some pretty solid footing in this case.

For years, we’ve talked about how FPGAs were trying to “replace ASICs.” In fact, ASIC replacement has been the battle cry of the FPGA companies for about as long as there have been FPGA companies. Every couple of years, with a new family based on a new process node, the FPGA companies come forth and say, “This time, we’ve done it. We’ve made an FPGA that can replace ASICs.”

 

Google's Smartphone Revolution

Inside Project Ara

by Amelia Dalton

A coup d'état is imminent. A mobile revolution. With "Modular!" banners held high and money where their mouths are, Google is marching through the streets determined to overthrow the status quo in smartphone technology. This week’s Fish Fry is all about Google’s Project Ara - why it's cool, why you should care about this modular smartphone technology, and how you can get started designing your OWN modules. My guests are Ara Knaian (NK Labs) and David Rutledge (CTO - Lattice Semiconductor) and we are going to talk about what's inside the Google Ara phone, the important role of FPGAs, and why Ara lent his name to this super cool new project. Also this week, we take a tour of Xilinx’s Vivado IDE and break the biggest news to hit the EE airwaves.

 

Toward Ten TeraFLOPS

Altera Kicks Up Floating Point

by Kevin Morris

The Cray-2, the world’s fastest computer until about 1990, was capable of almost 2 GigaFLOPS (Billion Floating Point Operations per Second) - at an inflation-adjusted price of over $30 million. A decade later, ASCI Red - selling for a cool $70 million or so - topped one teraFLOPS (Trillion Floating Point Operations per Second). The machine was twice as expensive, but the price per performance had dropped from ~$15M/GFLOPS (Cray) to ~$70K/GFLOPS (ASCI Red). That’s a shocking improvement. Moore’s Law would have us believe in a ~32x gain over the course of a decade, but real-world supercomputers delivered over 200x in just ten years. Take that, Dr Moore!

Sometime in 2015, according to Altera, we will have a single FPGA (yep, that’s right, one chip) - designed by Altera and manufactured by Intel - capable of approximately TEN teraFLOPS. Let’s do some math on that, shall we? We don’t know exactly what a Stratix 10 FPGA will cost, but it almost doesn’t matter. This device should put us in the realm of $1/GFLOPS. Or, compared to ASCI Red, an additional 70,000x improvement in cost per performance.

 

Programming QuickLogic’s Sensor Hub

Hardware from a Software Standpoint

by Bryon Moyer

Well, it seems to be sensor hub season. A couple of interesting things are brewing. One, in particular, is of strategic significance, and I’ll be writing that up once I get a chance to dig into some more details.

For today, we’re going to go tactical rather than strategic: we’re going to dig deeper into QuickLogic’s sensor hub solution. And we’re going to get our hands dirty. If you read my earlier piece on sensor hub partitioning, you’ll recall that QuickLogic has a rather intricate implementation that puts much of the sensor hub functionality in FPGA hardware using a combination of low-level software, state machines, and outright hardware. Their claim is that they can achieve the lowest power this way – lower than a more common microcontroller implementation.

 

Heartbleed: Serious Security Vulnerability

Serious Wake-up Call

by Bruce Kleinman, FSVadvisors, foreword by Kevin Morris

Imagine if you woke up one morning, and found out that Walmart was now selling a device for $5 that could easily and instantly open almost any deadbolt lock. That’s right - the kind of lock that is supposed to give “extra protection” to just about every door on earth. That’s the magnitude of security problem posed by the Heartbleed Bug.

Contributing columnist Bruce Kleinman wrote the first half of this article and posted it to his “From Silicon Valley” blog on April 6, 2014. The timing of the post was a remarkable coincidence: just 36 hours before the Heartbleed Bug started making headlines.

As the creators of technology, we engineers need to re-think our commitment to security and safety. The systems we design don’t just earn us money – they are often trusted to protect people’s lives, privacy, and assets. This is a solemn responsibility that is all too often overlooked or given short shrift in our ongoing race to get timing closure, first silicon, working prototypes, and volume shipments.

 

“Softly” Defined Networks

Xilinx Punches Up the Programmability

by Kevin Morris

Programmability is a powerful concept. It allows us to build a physical machine and then modify, upgrade, repurpose, repair, and evolve it - without having to alter the original physical hardware. It allows us to design one device to serve multiple purposes, with variants, upgrades, and value-added features enabled with the flip of a few bits. Programmability extends the life of equipment in the field, reduces inventory requirements, simplifies maintenance and diagnostics, and often eliminates the need to roll a service truck altogether.

In the world of networking, programmability promises these enormous benefits in the extreme. With the global bandwidth glut, network build-out has been a high-stakes, high-priority, big-revenue, full-throttle enterprise for the past three decades - and it shows no signs of letting up anytime soon. If you’re designing network hardware, you already know the drill. You design around the bleeding-edge of what’s possible with current hardware, often against standards that are still in flux, in a race against other companies’ engineering teams that are just as daring and terrified as you are.

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