Five Ways to Build Flexibility into Industrial Applications with FPGAs
As industrial system complexity increases, FPGAs offer the ability to integrate an entire system on a chip (SoC), at a lower cost compared to discrete MCU, DSP, ASSP, or ASIC solutions. This document describes using an Altera industrial-grade FPGA as a coprocessor or SoC to bring flexibility to industrial applications. Providing a single, highly integrated platform for multiple industrial products, Altera FPGAs can substantially reduce development time and risk.
White Paper sponsored by Altera
Smart, Scalable Debugging with ZeBu
Modern SOC realization requires a development effort beyond that of traditional hardware verification. Creating a complete application-ready SOC platform now includes pre-tapeout software validation and hardware/software co-verification using full-chip RTL models. These billion-cycle scenarios are often beyond the scope of HDL simulation, but are ideal for emulation using EVE’s ZeBu hardware-assisted verification platforms.
White Paper sponsored by EvE
Choice of an ISA for Embedded Designs
Software investment is the biggest ticket item in any project. Hence the choice of an ISA that offers a scalable solution is an important consideration. MIPS and our SoC eco system offer distinct families of processor cores that span from 32-bit micro controllers all the way to 64-bit multi-threaded super-scalar cores from single-core to many cores, to address various segments of the embedded markets. For either a new design or a follow on or upgrade to an existing design, the choice of MIPS as the ISA offers an ideal path for protecting the software investment on a project, since one can scale the application up and down the performance scale seamlessly between a wide range of processors. The bulk of the effort in the migration to any new ISA is in the low-level initialization software. This paper illustrates the ease of migration from the ARM to MIPS architecture and highlight the areas that users need to focus on.
White Paper sponsored by MIPS
Optimizing Performance, Power, and Area in SoC Designs Using MIPS® Multi-threaded Processors
Hardware-based multi-threading technology has for some time been known in the industry as a feasible technique for improving system performance, but not too many people are aware of just how much traction the technology has gained since its early implementations in the 1960s. This article provides a brief history of hardware based multi-threading and some examples of its commercial adoption so far. It then gives an overview of the fundamental value of multi-threading in hardware, and describes MIPS Technologies’ multi-threading architecture and product offerings. The article also provides several multi-threaded application examples—including those in the areas of driver assistance systems and home gateways—to demonstrate the broad applicability of multi-threading in real-world applications.
White Paper sponsored by MIPS
FPGA Design Methods for Fast Turnaround
This paper takes an in depth look at a variety of techniques to help you speed up your synthesis iterations. Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.
White Paper sponsored by Synopsys
FPGA - PCB Co-Design Done The Right Way
Join Amelia Dalton as she talks with Hemant Shah of Cadence Design Systems about new ways to manage the complex issues that arise when trying to optimize pin assignments for both FPGAs and PCBs.
Chalk Talk sponsored by Cadence
Reliable Reset Generation for TI DSP Processors
Every requires a reset generator circuit or IC to start up from a fixed condition after the supplies are turned on, and prevent the processor from executing instructions incorrectly and causing flash memory corruption. Traditional, simple, single-supply reset generators were adequate for single supply processors, but no longer are sufficient to guarantee reliable operation of multiple supply processors. This white paper examines some of the challenges associated with resetting modern processors.
White Paper sponsored by Lattice
Hierarchical Design Flows: Design Preservation & Team Design
In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.
Chalk Talk sponsored by Xilinx
System-Level Debugging and Monitoring of FPGA Designs
This white paper describes the latest state-of-the-art methods for debugging and monitoring large FPGA designs both during the simulation phase of development and after device configuration, and details the current practices that Altera has identified across a representative number of customer designs.
White Paper sponsored by Altera
ZeBu™: A Unified Verification Approach for Hardware Designers and Embedded Software Developers
Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools.
White Paper sponsored by EvE
Implementing Floating-Point DSP in an FPGA
Are you finding it challenging to efficiently implement floating-point digital signal processing (DSP) algorithms? Learn how Altera’s new floating-point design flow makes it easy and enables your designs to achieve high performance and efficiency.
Preparing for Google TV
Google and partners recently announced Google TV—an open, architecture-neutral platform that will bring the full web experience to television viewing. Given the fact that MIPS licensees lead in the digital home today, it is likely that there will be a large number of future Google TV systems based on the MIPS architecture. Leveraging our work with Android and our ongoing relationship with Google, MIPS is in an excellent position to work with our licensees as Google TV moves beyond initial reference platforms and into mainstream development within the digital home market. By designing your SoC to the right specifications now, you can be ahead of the market when the Google TV code is available in open source in 2011. In this paper, we will provide you with an in-depth description of hardware requirements and recommendations for developing an SoC that will support the Google TV operating system!
White Paper sponsored by MIPS
Applying the Benefits of Network on a Chip Architecture to FPGA System Design
NoC interconnect architectures provide a number of significant advantages over traditional, non-NoC interconnects, such as allowing independent layer design and optimization. Altera's Qsys system integration tool, included with the Quartus® II software, generates a flexible FPGA-optimized NoC implementation automatically, based on the requirements of the application.
White Paper sponsored by Altera
“Smart” Connected Home Entertainment with Android
Experience the SmartCE (Connected Entertainment) for Android platform from MIPS Technologies in this new video demonstration. The SmartCE Platform enables MIPS licensees and their customers to bring differentiated connected entertainment solutions to market quickly.
Spartan-6 FPGAs in Video Designs
In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.
Chalk Talk sponsored by Xilinx