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FPGA Synthesis Showdown

Kevin,

I'm curious. Can you actually be honest with your EE Journal readers?

Can you admit that you were essentially fired at Mentor Graphics?

Isn't that the truth?

Actually what I heard is you were put in charge of nobody. That is typically t…

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A Non-FinFET Path to 10 nm

FD-SOI is better than FinFET for a couple of reasons, one being you can switch between high-power/performance to low-power/performance just by changing the back-biasing, whereas FinFETs would need to use DVFS, i.e. if you just use clock gating in a design…

2
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The Internet of Seeing Things

Kevin:

Intelligent Vision or "Embedded Vision" is the killer app that I had in mind when we started developing ZYNQ at Xilinx in 2008 ! In 2011, Jeff Bier and I started the Embedded Vision Alliance to help educate and teach developers how to add Intel…

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A 1T (or 2T) SRAM Bit Cell

In terms of functionality, you're correct that it can be thought of as 3T. However, with regards to the area footprint, it is 1T (the cell size at 28 nm is 0.025um2, compared with 6T size of 0.127um2). The schematic cell drawing in this article includes a…

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Who Owns the IoT Gateway?

What do you think the future configuration of the IoT gateway will be like?

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High-Level Design for Everyone

Highlevel Language Design Methodologies sounds great to me.
One question: Why only C and C++ as the highlevel languages?
Wouldn't there be interest in using languages like Java, Python, Scala, Clojure etc. for direct FPGA synthesis. If a couple highlev…

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