14
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The FPGA Tool Problem

If you look at ASIC design in Wikipedia, functional verification is done before synthesis and includes logic simulation.
Altera ModelSim requires a netlist created in the compile step which includes synthesis and probably place and rout.
Meanwhile only …

1
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Organically-Shaped Antennas

What do you think about antennas shaped according to the Superformula?

6
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Intel’s First FPGAs

tails wrote "The back-end in this case would still be the custom place-and-route tools provided by the vendor. So I'm all in favour of open-sourcing the tools - but the right part should be exposed, at least initially. "

I agree because the existing to…

3
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Xilinx vs Intel

Hey Kevin, I was kind of surprised you didn't throw Xilinx's SDSoC into the conversation - not that it's some kind of magic wand/potion, but I'd be interested to hear your thoughts on the tool as it pertains to the C/C++ --> HDL 'dream'... I seem to vague…

1
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Abstracting Register Sequences

What do you think of Agnisys's approach to register sequence specification?

1
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Interim Industrial Security

What do you think of Icon Labs' approach to securing old networked industrial equipment?

2
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Humans vs. Computers

Of course if they are using internet available data to authenticate, well hummm. And Yes, I'm old enough that my childhood address is probably not on the internet but that's probably not true for a majority already. As we lose more and more privacy to …

1
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New SRAMs Popping Up

What do you think of the SureCore and Mentor SRAM innovations?

2
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FPGAs for the Masses?

"The implementation is correct by construction, so there is no need for hardware level verification and debugging."

This is the way that design should be done. It is up to the design tools to accurately implement the logic and data flow.

HW timing …

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