What Happens to FPGA?
For decades, the FPGA market has been a well-balanced duopoly. Something like 80% of sales have been split by two ferocious competitors, Xilinx and Altera, constantly jousting for single points of relative market share. This dynamic has driven everything from the FPGA technology itself to the tools, IP, and services that make the whole concept work. It has determined what we pay for FPGAs, what they can do, and how we use them.
Now, Intel plans to buy Altera, and the duopoly that has dominated the FPGA universe will come to an end. What happens next? Will the Earth shift on its axis? Will the “FPGA market” cease to exist? What will be the long-term implications of this business change on the future direction of this critically important technology?
Musings from the Design Automation Conference
I just returned from attending the 52nd annual Design Automation Conference (DAC) in San Francisco, CA. This was my 30th time to attend this event, so I’ve had more than a little time to contemplate what the whole thing is about. It is fascinating to me that DAC, which celebrates electronic design automation (EDA) - one of the most important enabling technology sectors in the advancement of Moore’s Law - began even before Gordon Moore’s prophetic article laid out the roadmap for the last 50 years of exponential progress in electronic technology.
Yep, DAC pre-dates Moore’s Law. Chew around on that one for a little bit.
DAC Takes On the City by the Bay
This week we're rockin' and rollin' in the key of IP with an EDA backbeat at the hottest design automation party of the year - DAC 2015. First up on stage is Mike Gianfagna from eSilicon who sings us a sweet little ditty about big data and tools that love it. Next up, we get all folksy with EDA consortium president Bob Smith. Bob serenades us with a song of innovation and collaboration that can only come from a motley band of many players. Lastly, I explore the underlying themes that define the chorus of this year's Design Automation Conference.
Sonics and Mentor Graphics Attack From Different Angles
PCs have a rudimentary form of power management. Under a limited set of circumstances, a PC can reduce its own power consumption without your manually having to put it to sleep. As far as my experience tells me, the events that can cause a power down are inactivity and lid closure. And the power savings can be obtained by turning off the display and entering a sleep or hibernate state. This is pretty much the extent of what’s possible using the top level of the Power Options utility.
But let’s say you want to be a good, safe computer user and back up your system. With many such systems, it’s easier to do this while you’re not using the computer. I’ve found one program, for instance, that can back up email files to the cloud. But each time you get an email, the email storage file changes, causing a backup restart that can block the backup of numerous other files.
Greed Trumps Vision in Technology Mergers
A technology company has a kind of soul - a manifestation of a tribal culture that has evolved and matured from the earliest days of its founding. Building a bright-eyed startup into a large, successful enterprise requires a unique cocktail of vision, boundless energy, and commonality of purpose that instills upon the team a distinct personality that is evidenced in everything it does.
In countries with, perhaps, a bit more rigor in their application of the English language than the United States, companies are referenced with the plural verb: “Google ARE launching a new product.” This is a subtle but constant reminder that a company is not a singularity, but a collective - a group of people who have come together in a unique way with a shared mission and a particular way of doing things. These people often spend more time with each other than they do with their own families, and their goals, behaviors, and ways of working and interacting are molded by membership in that group. In every sense of the word, a technology company is a tribe.
Where is the Real Value in Embedded Engineering?
“I suppose that even the most pleasurable of imaginable occupations, that of batting baseballs through the windows of the RCA Building, would pall a little as the days ran on.” – James Thurber
What do buses, windows, and iTunes have in common? They’re all engineering successes that don’t really look like, well, engineering successes.
This week I spoke with two different companies that sell on-chip networks for SoC designers. They’re IP companies, which is to say they license their R&D efforts to other hardware engineers in exchange for an upfront fee and a royalty. It’s a pretty well understood business model, so no surprises there.
Spectra-Q Accelerates Quartus II
When people are curious about the performance and capabilities of programmable logic products, they often get buried in the details of the datasheet. It’s easy to get wrapped up in debating LUT counts, Fmax numbers, and a bunch of other silicon-related esoterica that may have little to do with how well a particular device will perform in your application.
You know what matters a lot more than the details of the chips? The performance of the tools.
The under-appreciated universal truth of programmable logic is that tools usually have a lot more to do with the success of your design than the silicon does. Luckily, even though the customers don’t always understand this, the vendors certainly do. Altera and Xilinx each spend a substantial share of their engineering budgets developing and improving their tools in order to gain a competitive advantage and make their customers more successful with their devices.
Mentor’s xACT Wrestles with FinFETs, Corners
So you build a circuit with a couple of transistors here and a couple of transistors there and you want to see how it’s going to operate. So you’ll simulate (or do signal integrity analysis or whatever other study you’re interested in). But you need to tell the tool about your circuit. So… do you just say, “Yeah, I’ve got a couple transistors here and a couple resistors there – please go calculate”?
Ah, if only it were so simple. Of course that won’t work – because it ignores all of the unstated interactions between the elements and other parasitic structures in the silicon substrate. Back when circuits were small, that meant manually building a more complete model that included the extra resistors and capacitors (and perhaps the occasional inductor) and putting that whole thing through the tool.
2015 Design Automation Conference Preview
It's that time of year again. Ring the bells, sound the alarm, and roll out the red carpet - it's DAC time! In this week's Fish Fry, Anne Cirkel (General Chair - DAC 2015) gives us a special sneak peek into the biggest EDA conference of the year - The Design Automation Conference. Anne dishes the details of the conference: the super cool keynotes, the "I Love DAC" program, and the inside info on the best parties at this year's show. Also this week, we examine a unique Kickstarter campaign that marries nanotechnology with fashion to create this season's must have: The Unstainable™ White Shirt.
Mentor PADS Redefines the Board Genre
Anybody who has ever bought professional PCB software has probably noticed a problem with the way PCB tools have always been packaged, priced, and marketed. Well, anybody except for the folks who actually sell PCB tools, that is. For some reason, PCB tools have always been sold with a built-in wrong assumption - that only big companies with large design teams are doing sophisticated designs. If you were a huge company with giant design teams that required all the “enterprise” features related to team design, collaboration, IP sharing, and library management, the PCB tool vendors gave you all the features needed for leading-edge, high-performance board design.
But, if you were a smaller company or team who didn’t require all the big collaboration features, you got the toy-like “desktop” PCB tools which didn’t include the stuff you needed for high-performance, high-density board design.
Moore’s Law Turns Fifty
It’s been a half-century since Gordon Moore published “Cramming More Components Onto Integrated Circuits” in the April 19, 1965 edition of Electronics Magazine. It was another five years before Carver Mead dubbed Moore’s prediction in that article - about progress in integrated circuit density - “Moore’s Law,” and another five years after that before Moore revised his original “doubling every year” prediction to “doubling every two years.” At its simplest level, then, Moore’s Law predicts that the number of transistors that can be fabricated on a single chip will double every two years.
The fifty years that have followed that prophetic piece have seen nothing short of the most amazing advances in human history. Moore originally predicted that the trend would continue for “at least ten years,” but the exponential he foresaw has held almost miraculously steady for five times that long. Some would say that Moore brought incredible insight with his prediction. Others would say he was lucky. Still others would claim that this is an example of self-fulfilling prophecy. Whatever the case, the profound impact of that one metric - “number of transistors on a single chip” - on just about every aspect of our global society is almost unfathomable.
The changing role of European Funding for Embedded Systems R&D
The European Union (EU) is a complicated beast. It isn't a United States of Europe, although in some lights it can look like it, as it has laws that overrule those of member states, and it uses a common currency (although not all member states use the Euro).
Its roots are in the devastation of the Second World War, when a shattered Europe was rebuilding its industrial base and at the same time looking for ways to ensure that there would never again be conflict between European countries. It has been successful in both those aims and has taken on increasing powers as it has expanded to include 28 countries. It is now a single market with no customs duties or protectionist measures and, with the addition of Switzerland, Norway and some "micro states" like the Vatican, is a passport free area, except for the Republic of Ireland and the United Kingdom. One task of the EU is to improve the competitive position of European industries, particularly those that are seen as important to future growth, such as electronics.
Cadence Launches Innovus
It’s a familiar tale of woe: new silicon process nodes are creating an extreme burden for design tools.
When I say, “familiar,” it’s not just because everyone is bemoaning the current state of affairs, what with FinFETs and multiple patterning and other new features creating innumerable vexations. No, it seems that this happens after every few advances: the improvements made to nullify the last set of hurdles run out of steam in the face of the latest set of new hurdles. And so tools get rolled again.
The product of the tools – a correct mask set – hasn’t changed; the ways we get to that mask set have changed over and over. And continue to do so.
Taming the Wild West of EDA Design with OneSpin
This week we’re saddling up and taking a ride into the Wild West, where the days are long and the code is even longer. We’re talking about the rough and tumble, SystemC slingin’, HLS wranglin’ assertion-based formal verification. Dave Kelf (OneSpin Solutions) rides with us across the dusty EDA plains of RTL design where we unveil why RTL (and above) is called the Wild West of Design, who exactly is playing sheriff in these here parts, and how design and verification at the RTL level can be corralled once and for all. Also this week, we address the most recent rumors surrounding the Intel/Altera buyout deal and investigate the newest (and coolest) smartwatch this side of the Mississippi - an Enigma machine for your wrist!
Cadence Stratus Ushers In a New Era
It’s been more than twenty years since I started working on high-level synthesis (HLS). You might say I’ve studied the topic a lot. For most of those two-plus decades, HLS has been widely considered the “design methodology of the future.” And there are those who have held onto the belief that it always will be.
For those of you not in tune with the terms, high-level synthesis is the automatic creation of hardware architectures from behavioral descriptions. At first, HLS was known as “behavioral synthesis.” But, after some early bad experiences, the EDA industry quietly shifted the name over to HLS - hoping that nobody would notice or have episodes of PTSD when confronted with the idea.