Proliferating Programmability in 2014

Forecasting the FPGA Future

by Kevin Morris

The ball has dropped, the bubbly sipped, and the resolutions resolved. 2013 has ended, and before us we have a new year, a new universe of opportunity, and a crazy cauldron of activity in our beloved world of programmable logic. It’s time to throw down, gaze into the crystal ball, read the tea leaves, interpret the Tarot, and extrapolate the trend lines. Here, then, is our unflinching forecast for FPGAs in the months and years to come.

Before we fire up our forecast fest, we should nail down what we mean by “FPGA.” After all, the definition has been morphing, expanding, and shifting over the years, and even the companies with thousands of employees dedicated to nothing but making and selling FPGAs don’t seem to agree on the current meaning of the acronym. Ours will be simple - if it has a look-up-table (LUT) cell, it is an FPGA. (Yes, we hear the screams out there. Bear with us. It will all come out in the wash.)

 

The Year in EDA

Did Anything Happen?

by Bryon Moyer

2013 is coming to a close, and this is usually a time for reflecting on what’s happened in the past year and what’s going to happen in the coming year. The thing is, though, when I sit back and reflect, well, I don’t know; it just seems like 2013 was a quiet year for EDA.

So I took a couple of approaches to reviewing the year. One is to see what the Big Guys did and the other was to solicit some other opinions as to what’s in and what’s out.

 

Hackers, Makers, and Teachers

Ben Heck, UVM Primer, and Printing with Metal

by Amelia Dalton

The year is drawing to a close, and the snow is falling, but the friday fun is just heatin' up. Our first guest is none other than Ben Heck from element14's wildly popular engineering television series "The Ben Heck Show". Ben gives us an exclusive preview of the next season of "The Ben Heck Show" and lets us in on how he got into this crazy business. Also this week, author Ray Salemi is here to light our way to a special place called UVM land. He's written a new book called "The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology" and he's here to break UVM down into its geeky bits and pieces. Finally, we close up this week's Fish Fry with a discussion about some innovative open source plans that could bring 3D metal printing right to your work bench. Saddle up, my friends, the fun is about to begin!

 

X-Verification Methodology for Both Designers and Verification Engineers

by Lisa Piper, Real Intent

The propagation of unknown (X) states has become a more urgent issue with the move toward billion-gate SoC designs. The sheer complexity and the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final silicon. This article describes a methodology that enables design and verification engineers to focus on the X states that represent a real risk, and to set aside those that are artifacts of the design process. The goal is to reduce project time, particularly time spent in simulation, and overcome the limitations at both the RTL and gate level.

X proliferation

Billion-gate designs have millions of flip flops to initialize. Many of the IP blocks used in such designs also have their own initialization schemes.

 

Altium Bends Over Backward

Plays to its Base with AD14

by Kevin Morris

The headline new feature for Altium’s newly released Altium Designer 14 (AD 14) is “Rigid-Flex Support.” True, rigid-flex is there, and it’s cool, but the headline might lead the casual reader to miss some very important changes that are happening at Altium. Altium has a new focus and a new mission these days. The Altium folks are going back to their roots, playing to their base, and trying to re-establish a strong partnership with the engineers the company was created to serve - the common, hard-working, in-the-trenches, everyday designers who are trying to create cool stuff but who don’t have the resources for the fantastically-expensive, enterprise-oriented PCB solutions from the likes of Mentor and Cadence.

For the past several years, Altium has been a bit like that genius ADD kid in the back of the classroom - full of brilliant ideas, but not at all focused on what is going on in class at the time. Altium has suffered from, if anything, an excess of forward-thinking vision - leading their customers with fascinating new design paradigm ideas and features, but failing them somewhat in delivering rock-solid implementation of the day-to-day, pedestrian PCB design capabilities needed for plain-old place-and-route. The rub on the street about Altium was that they were too focused on the flashy and not enough on fixing old bugs.

 

A Happier Muse

Can Cadence’s Voltus Make Us Less Pessimistic?

by Bryon Moyer

Many of the arts and skills developed throughout the ages have credited much of their inspiration to muses and patron saints and gods and spirits. These other-worldly beings provided both inspiration and guidance as the artisans built up a vast cultural legacy going back millennia.

So… if there’s a muse for engineering, who would it be? The thing about engineering is that free flights of fancy are often not permitted. We’re constrained by the possible, in stark contrast to experimental artists and even pure scientists. In fact, it’s worse than that: we have to make money. Usually for someone else. Which puts a further damper on things. Stuff has to work under a wide range of conditions, some predictable, some not.

 

A Look Into How a High-Level Synthesis Design Flow Benefits Verification Turnaround

by Phil Bishop, Cadence Design Systems

The design and re-use productivity benefits of SystemC-based high-level-synthesis (HLS) are generally well understood. However, a major benefit of moving to this level of design that is rarely explored is improved verification turnaround and productivity.

Most system-on-chip (SoC) design flows employ SystemC transaction-level models (TLM) to create virtual prototypes. These virtual prototypes are used to verify the ever-increasing degree of software content. The utilization of SystemC models in the design flow forms an approach that Jim Ready, Cadence’s chief technology advisor for software and embedded systems, refers to as “software-driven SoC development”.

 

3D IC Flow Challenges

Cadence Talks About the Toughest Bits

by Bryon Moyer

Cadence recently announced a design flow for CoWoS 3D ICs. We’ve looked at some of the issues surrounding 3D IC technology before, but what we’ve looked at less are the specific ways designers will implement 3D ICs within their EDA flows.

So I talked with Cadence’s Brandon Wang to see what specific challenges they encountered and addressed in the flow that they announced. He listed three primary elements: heat, testing, and stress.

 

Your Power Plane or Mine?

by Amelia Dalton

Do not pass go. Do not collect $200. Go directly to the power plane. Whether we like it or not, power integrity analysis is now a bigger (and messier) part of our PCB design process. In this week's Fish Fry, we get down to the bare metal of those pesky power planes with Brad Griffin of Cadence. Also this week, we check out a super cool new 3D printed robot (yes, you want one) and investigate what sets this little cutie apart from other humanoid robots.

 

It's an Analog World - Even for Digital Folks

Signal- and Power-Integrity Take Center Stage

by Kevin Morris

Let’s face it, we went to school and studied logic design because we really didn’t want to deal with analog stuff. As digital designers, we prefer our signals to have nice discrete values and to stay out of those fuzzy grey areas. We may have even settled into a clean, orderly area of engineering like FPGA design - just to preserve a firewall between us and that nasty curvy stuff.

Then, of course, our arrogant “need for speed” brought us to things like multi-gigabit serial interfaces. Suddenly, what should have been a well-behaved sequence of zeroes and ones took on a suspicious likeness to those wavy analog lines we were trying to avoid in the first place. We justified it by pointing to the benefits of getting rid of all those unsightly parallel busses. Still, terms like “eye diagram” entered our vernacular - and the next thing you know, somebody was talking about signal integrity. Yuk!

 

The Evil Twin Gets Evil

Unraveling SADP Part 2

by Bryon Moyer

This is the second part in our two-part series on the SADP version of double-patterning. I’d make some crack about your brains having recovered after Part 1, but realistically, despite all my overdramatic whining, that wasn’t that bad. That was the easy part.

In the first part, we looked at fundamental SADP concepts. (If you haven’t read it and this is new to you, I highly recommend…) But in the interest of focusing on the basics, I took some liberties (which I noted) that we now need to address. Now we need to figure out how to create an actual mask. This is where things start to look more evil.

 

Ten Years

Happy Birthday to Us

by Kevin Morris

Ten years ago, we had a vision - a vision of a new kind of trade publication: one that was completely digital; one that gave top-quality objective analysis and editorial on the electronics industry; one with a personality and a sense of humor that made professional engineering articles fun and interesting as well as informative; one staffed by people with firsthand experience in the engineering trenches and deep knowledge of the industry.

Then, we said, “Nah,” and created this one instead.

OK, kidding aside, this is our ten-year anniversary and we wanted to at least build a little digital bonfire and sit around it talking about the old days when we did three-micron tapeouts with actual tape, and when we put green magic marker around the edge of our software CDs in hopes of reducing the number of bugs. (Hey, if it was supposed to make CD music sound better, worth a try, right?)

 

Cadence Gets Their Funny On

Unhinged with Brian Fuller

by Amelia Dalton

Who said electronic engineering can't be funny? (Someone who has never read this publication!) In this week's Fish Fry, we check out a brand new online television show that that aims to bring the saucy style of late night television talk shows to our engineering community. My guest is Brian Fuller of Cadence Design Systems, and we chat about why Cadence decided to make a humorous engineering-based talk show and how they are going about the business of making EE fun.

 

Double-Patterning’s Evil Twin

Unraveling SADP – Part 1

by Bryon Moyer

What follows is something I enter into with great trepidation. Getting this… article thing… to a point where you can read it has involved more brain cell abuse than I inflicted upon myself during my entire college career. OK, it sort of feels like that, anyway.

We’re going to talk about double-patterning. Yeah, I know, we’ve talked about it before and it wasn’t so bad, was it? Ah, that’s because there isn’t just one double-patterning: there are two. Actually, there are more than two, but most of the other major variants don’t seem to be finding their way into production, so we’re going to ignore them. Denial being an awesome tool when used the right way.

 

Ensuring Design Reliability with Design Patterns

The Designer's Perspective

by Dina Medhat, Mentor Graphics

Circuit reliability verification has become a crucial step in IC design. Reliability requirements are not only growing in all market segments, including automotive/transportation, medical, mobile/wireless, and consumer electronics, but the complexity of today’s circuits is presenting unprecedented verification challenges. To get these designs to market in a timely manner, while ensuring they will perform as designed, designers need automated circuit reliability solutions that can quickly and accurately analyze these complex designs. From the designer’s perspective, two critical factors in efficient reliability verification are: • the ability to understand the logic of the circuit • the ability to recognize specific circuit topologies (patterns) associated with circuit reliability

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