The Big Game that Never Ends
I’ll be the first to admit that I don’t understand cricket, but I’m told that cricket matches can sometimes run for days on end, and that it’s often unclear who’s winning until, suddenly and unexpectedly, one team meets some arbitrary victory conditions and then goes home to celebrate with a few pints. The FPGA synthesis game is a lot like that. It’s a high-stakes game with vast amounts of revenue at stake, not to mention some serious technology bragging rights, but it’s never really clear who’s ahead, who’s behind, or even what the rules were in the first place. It’s been going on that way for something like twenty years, and despite fierce competition and incredible technological advances in the tools, the scoreboard is still basically a bunch of gibberish. Nonetheless, the audience is stuck on the edge of their seats (Maybe they’ve been Super Glued there?) watching every move in this weird and wacky contest between tool nerds that have never met.
GlobalFoundries’ FD-SOI Alternative
It was the coolest transistor development in many a year. Rather than continually squishing transistor parts closer and closer together, we flipped it to vertical and celebrated the arrival of the FinFET.
Which was great: it gave us a way to keep increasing performance in many of the applications where the value lies in the speed of the circuit. But after the initial party was over and we started picking up the pointy party hats and nursing the hangovers with massive doses of ibuprofen, we started looking at the bill. FinFET is nice, but it’s also expensive. And, while we’re throwing stones, it’s also not so great for analog and RF designers based on the quantized nature of the gate. You can’t increase channel dimensions by 1.5 times; it’s either 1 or 2.
ASML’s EUV Lithography Tools Push the Boundaries of Invisible
There aren’t many industries where 15 units qualifies as “a big order.”
Battleships. Nuclear power plants. And EUV tools.
For the 14,000 employees at Dutch lithography company ASML, 15 orders for EUV tools is a big deal. Even though that number spans five years and four generations of the company’s EUV equipment, it’s still considered “volume.” Walmart they ain’t.
EUV (extreme ultraviolet) lithography is still is bit space-age and sci-fi for many chipmakers. We’ve been shining DUV (deep ultraviolet) light on our chips for quite a while now, but the limits of that technology are making themselves known.
The Nature of a Bursty Business
Those of you who have been with us a long time may well remember that our humble journal didn’t start out as EE Journal. In fact, it started as FPGA Journal, with founder Kevin Morris as chief editor, writer, cook, and bottle washer. A few years later, we added a new Embedded Technology Journal (whose current embodiment is ably managed by Jim Turley). Only several years after that did we take on IC design specifically, which is when yours truly joined the fray.
And then we opened our umbrella wider, covered more topics, and consolidated into a single EE Journal, with a number of specialized “channels” that would allow our readers to on their specific areas of interest. Out of the IC newsletter were born two channels: EDA (for the tools) and Semiconductor (for the underlying silicon technology).
Xilinx Rolls Out HLx
For more than two decades, the promise of high-level design methodologies has been dangled in front of digital hardware designers. High-level design was going to revolutionize our design process. It would make us dramatically more productive. It would make us vastly more agile and adaptable as our design requirements evolved. It would make us into Super Engineers - or it would take away our jobs.
Everyone who has designed at the register-transfer level (RTL) using hardware description languages (HDLs) such as VHDL and Verilog knows, deep down in their bones, that RTL is not the answer. The detailed, nit-picky, verbose, cryptic, architecture-specific, technology-locked nature of RTL design is almost incomprehensibly clunky. Yet, for more than twenty years, it has persisted as “the way it’s done” when designing digital hardware.
Screens Will Cooperate Rather Than Compete for the Users' Attention
What is a K or k? If you are in the world of SI units, then k is the magnitude symbol for 103 (= 1,000). In computing, we are accustomed to K meaning 1024. So when you see 4K for a video standard should you be expecting 4000 or 4096 pixels horizontally? When you visit the cinema, then the 4K projector uses 4096 pixels, but if you are buying a new television badged as 4K then you will get a screen that is only 3840 pixels wide! The new Ultra High Definition (UHD) screens that TV manufacturers want you to buy this shopping season have a screen definition of 3840 by 2160 pixels – just double the HDTV standard of 1920 pixels.
But UHD TV screens are just one part of today's multi-screen world. How many screens do you own? The man who was sitting opposite me on the train today had four on the table: two cell phones, an e-book reader and a laptop computer.
Surfing the New Innovation Wave
Consolidation, consolidation, consolidation. If you’ve been following the news in the semiconductor market this past year, you’ve seen acquisition after acquisition. There is no doubt that there is a big consolidation underway in the semi space. And consolidation is nothing new. We have watched little semiconductor companies join to become bigger and bigger semiconductor companies for years.
But this time, it’s different.
The IIC Tries to Think of Everything
Deep in the heart of Portland or Austin or Minneapolis or any of dozens of towns across the nation and the world, Makers are busily building components for the Internet of Things (IoT). Long dismissed as hobbyists unworthy of sales attention, many of these skilled designers are where the IoT rubber hits the road.
Way on the other end of abstraction, folks in the Industrial Internet Consortium (IIC) have been expending much effort trying to lay out an IoT framework that might promote interoperability and numerous other desirable traits. Many of these abstract characteristics may, at some point, be implemented in a concrete fashion by one of those engineers.
EDA, Piracy, and the Stormy Seas Ahead
Their bow shreds the digital waves like a knife. They will take no prisoners. It’s the thrill of the kill they seek and they will stop at nothing until the software is theirs. In this week’s Fish Fry, we are thwarting those dastardly cyber pirates with a mighty sword - a SmartFlow sword. Ted Miracco, CEO of SmartFlow Compliance Solutions, joins Fish Fry and we’re diving into the deep murky waters of cyber security in high tech. (I also ask him what’s it’s like to play football with Alec Baldwin!) Also this week, we check out a new retro DIY gaming system on Kickstarter called Tiny Arcade.
No Apparent Loss, But What Does It Mean?
Synopsys has joined an illustrious list of high-value names that are members of a growing club: companies that have been hacked.
This week they announced an unauthorized breach in their “EDA, IP and optical products and product license files through its customer-facing license and product delivery system.” They were careful to note that “no customer project or design data in this system was accessed, and there is no indication that this incident affected any other Synopsys systems.” And, critically, “The license and product delivery system does not store personally identifiable information (PII) or payment card information (PCI).” And that they’ve closed the means of access that was used.
I was able to chat with Synopsys’s Dave DeMaria to get a better understanding of what happened. So let’s start by laying out the situation.
Altera Kicks Up the Tools
It can be tough being in the lead. For years, one of the brightest spots for Altera Corporation in the FPGA market competition with archrival Xilinx, Inc. has been their Quartus II tool suite. It’s no secret that Xilinx struggled with their old ISE tools, ultimately leading to a complete, ground-up redesign. Altera’s Quartus II continued doing its job, while Xilinx had the “new shiny object” - with all the excitement and problems that go along with re-designed tools.
But, what then do you do if you’re Altera? You’ve been ahead in tools for years, your customers are pretty happy with Quartus II, and they’ve invested a lot learning to use it effectively. Your competitor (and their customers) have bitten the bullet and started from scratch with a new but modern tool suite. You don’t want to disrupt the good thing you’ve got going with Quartus II, but neither do you want to have the perception that you’re the ones with the “old” tools. You’re in a bit of a pickle.
The Key to Optimizing the Value of Hardware Design and Verification Engineers
The electronics and semiconductor markets have always been very competitive, and the ongoing consolidation trend has raised the stakes even higher. Additionally, significant investments must be made and requirements set well before the first unit ships. This up-front effort contributes significantly to the electronics value chain, where concepts and algorithms are invented and implemented as hardware or software. The hardware side is especially challenging due to its permanency and per-unit variable cost. The task of the hardware engineering team is to implement those concepts and algorithms in competitive and cost-effective silicon and to exhaustively verify that it will function as intended in every scenario.
Audio Weaver Claims Big Development Savings
One way of looking at the Internet of Things (IoT) is to think of it as endowing machines with human characteristics – in particular with respect to our ability to sense the world. To some extent, past efforts have served to sense things that we’re not so good at sensing precisely ourselves. Like temperature or pressure or orientation.
That helps humans, who can then combine their own senses with machine senses for better decisions. But if we further enable our machines to do what we can do, then we can have the machines do without us. (I know… not so good for jobs…). So cameras and microphones will replace our eyes and ears, playing an increasingly important role as our ability to process their data improves.
A Path to Flexible System Implementation
Firstly – if you are an existing FPGA user, you may not find much that is new in this piece, but really, it is not aimed at you. What would be useful is if you share it with your system architect colleagues and your software colleagues, for whom much of this may well be new and useful.
You are beginning a new project - let's say a motor control system. You can assemble components on a board – possibly a processor, a DSP, an FPGA for peripherals, and a networking ASIC. The result is a relatively large board, with the inherent reliability issues and a high BoM cost
Intel… Then What?
We wrote a lot in these pages (even long before it happened) about the market and technology trends and pressures that led to Intel’s bid to acquire Altera. We dove into the data center and dug up the game-changing combination of conventional processors with FPGA fabric that can form a heterogeneous computing engine, which could conquer the current plague of power problems that limit the size and capacity of server farms around the world. We argued that Intel needed Altera - as a strategic defense to protect its dominance of the data center in a future world where FPGA-accelerated processing was the norm rather than the exception.
Intel came, offered, negotiated, and eventually won. Now, pending approval of various worldwide regulatory bodies, Altera will most likely become part of the world’s largest semiconductor company. But what then?