To Grandma's PCB We Go
This week’s Fish Fry is all about your next PCB design. From power integrity to mixed-signal place and route, from Gerber files to schematics, from output pins over the FR4 and through the vias, to grandma’s house we go. My first guest this week is Greg Lebsack from Tanner EDA, and we discuss why you want a digital place and route tool, integrating ye ol’ analog into your next design, and what Tanner EDA brings to the mixed-signal party. Next up, we bring in Hemant Shah from Cadence Design Systems to chat about one of the biggest pain points of PCB design: the hand off to manufacturing. Hemant and I investigate a rapidly expanding industry consortium that is hoping to change all of that awful file hand off once and for all.
Or, How the Heck Do I Design a Photonic Circuit?
Several weeks ago we took a look at the expanding role of EDA. And then a couple weeks ago we delved into the bizarre world of silicon photonics. Yeah, we didn’t get too deep because the bottom drops off pretty quickly, and I’m not sure I could tread water credibly any deeper. But we got a flavor.
So now, we bring these two things together to answer the question, “If I’m going to be involved in a photonic chip design, what tools am I going to use?” OK, so if you’re an electronics designer, you’ll probably be asking the question, “What tools will the photonics pholks be using, and how will thier world interface to mine?”
Folks have been doing silicon photonics research for a long time now, and you need tools to do that. So it’s not like we’re just now seeing the emergence of new tools for this purpose. The thing is, there’s not a lot of profit in research, so the big guys that are commercially driven may not be attracted to such new endeavors in the early stages.
Carbon’s New Virtual Prototype Portal and UDG’s New Smart Robot
What’s the difference between a human and a pile of rocks? A robot algorithm (of course)! In this week’s episode of Fish Fry, we check out a new robot being developed at the University of Guadalajara that utilizes a pattern recognition algorithm to determine the silhouette of a human body. Also this week, we talk about the trials and tribulations of SoC design with Bill Neifert of Carbon Design Systems. Bill and I discuss Carbon's focus on the automatic creation of RTL-accurate models for integration into SoC designs and how you can make your IP configuration options a whole bunch easier.
Newer Tools Let You Do More than Just Electronics
Welcome to autumn. It’s usually a busy season – although the activity typically starts more with the onset of September and the resumption of school than with the equinox. But it also comes on the heels of a quiet season, even in the overworked US.
And EDA has seemed moderately quiet. So I started looking around to see what I might have been missing, and I’m not sure there’s a lot. But it did get me musing on why things might be quiet for the moment as well as what fills the gap – which gets to the topic of what qualifies as EDA. It’s more than you might think.
At the risk of being obviously over-simple, the legions of coders in EDA-land are doing one of two things: building new technologies or improving on old ones. The new technology category might include support for FinFETs or multi-patterning or the design kits for the latest silicon node. The improvement side of the tree is where performance and capacity and usability are juiced up – all in the name of productivity, of course.
Designing Code, Breaking Code, and the Verification in Between
Like the venerable Kenny Rogers once said, “You have to know when to hold ‘em, know when to fold ‘em…” In the verification game, much is the same. You have to know how to make the code, and you have to know how to break it. In this week’s Fish Fry, David Hsu (Synopsys) joins us to discuss the challenges of static verification and formal verification, how to “shift left”, and how to make code just to break it. Also this week, we investigate how hierarchical timing analysis may solve your sign-off timing troubles once and and for all.
Helpful Hot-Rodding Hints
Most of us engineers are at least closet hot-rodders. It’s in our DNA. No matter how good a contraption is from the factory, we just can’t resist the temptation to tweak a few things in our own special way, and often that’s all about speed.
FPGA design, it turns out, is a big ‘ol blank canvas for hot-rodding. Even though we (fortunately) don’t have glossy convenience-store magazines adorned with scantily-clad models standing next to the latest tricked-out dev boards, FPGAs have all the tools we need to rev our creative motors in the never-ending quest for that extra little bit of personalized performance.
But, where do we start? Do FPGAs have a set of go-to hop-ups? Is there a “chopping and channeling” baseline for programmable logic design?
It turns out the answer is “yes.” And, just to get you started, here are five tips for turning up the boost on your next project:
Ecosystem for Interposer-based Design?
We’ve talked a lot lately in these pages about the impending demise of Moore’s Law. Consensus is that, somewhere around the half-century mark, one of the most astounding prophecies in human history will have finally run its course. Next year, we’ll have a round of FinFET devices that will be so exotic and expensive that only a handful of companies will be able to use them. In the decade that follows, we may or may not reach 10nm and 7nm production - using either esoteric unlikelies like EUV or extreme-brute-force multi-patterning techniques - to solve just some of the multitude of barriers to continued downscaling.
Sci-fi techniques like carbon nanotubes, graphene-based devices, quantum computing, and that other-one-you-read-about are so far from production practicality that we may not see any of them in widespread use in our lifetimes. While incredible research shows great promise for many of these ideas, they are all back in the silicon-equivalent of the early 1960s in their evolution. The time and engineering it will take them to catch up with and eventually surpass what we can do with silicon today is substantial.
HLS and Sub-atomic Particle Jitter
Dateline: The 5th of September. Time: 2100 hours. We're on the hunt. No, we’re not hunting the mysterious Yeti, the Loch Ness monster, or heck even the ever-elusive EUV. This time, we're looking for some HLS. My guest this week is Mark Milligan from Calypto. Mark joins Fish Fry for the very first time to bring HLS into the light, into the world, and into the caring hands... of Google? Oh yes. Also this week, we delve into the deeply nerdy realm of sub-atomic particle jitter and investigate how the U.S. Department of Energy's Fermi National Accelerator Laboratory is hoping to solve an age-old existential question: How many dimensions do we really live in? (Spoiler alert: The space-time continuum may actually be a quantum system made up of countless tiny bits of information.)
Mentor’s RealTime Designer Rises to RTL
There are a lot of reasons why we can create so much circuitry on a single piece of silicon. Obvious ones include hard work developing processes that make it theoretically doable. But someone still has to do the design. So if I had to pick one word to describe why we can do this, it would be “abstraction.” And that’s all about the tools.
In fact, my first job out of college came courtesy of abstraction. Prior to that, using programmable logic involved figuring out the behavior you wanted, establishing (and re-establishing) Boolean equations that described the desired behavior, optimizing and minimizing those equations manually, and then figuring out which individual fuses needed to be blown in order to implement those equations. From that fuse map, a programmer (the hardware kind) could configure a device, which you could then use to figure out… that it’s not working quite like you wanted, allowing you to throw the one-time-programmable device away and try again.
Advanced vs. Established Process Geometries
It's time to saddle up and ride into the semiconductor sunset! Whether you're hitchin' your wagon to a young whipper-snapper node, or lassoin' a long-in-the-tooth workhorse process, the time it takes to get your IC design up and out of the corral may depend more on the software you use to verify your design than on the silicon itself. In this week's Fish Fry, Mary Ann White (Synopsys) and I get down to the very heart of semiconductor design: process geometries. We have ourselves a good ol' time chatting about challenges of FinFET designs, the tricky bits of working with both advanced and established process nodes, and how the right tools can make all the difference when it comes to winning the big product-to-market rodeo.
What if it Happened Again?
We sit here in our dazed, progress-drunk technology buzz looking back at the half-century rocket ride that transformed not only our industry and engineering profession, but also all of modern civilization. Nothing in recorded history has had as much impact on the world as Moore’s Law. It has re-shaped global culture, dramatically altered politics, and even affected fundamental aspects of the ways human beings work, think, feel, and relate to each other. If this weren’t the single biggest change driver in the history of civilization, it was right up there with democracy, monotheism, combining caramel and chocolate, and some other really heavy-hitters. Innovation in electronics has spilled over into just about every other aspect of our collective lives, and the change is profound.
But, what if it happened again - not in electronics this time, but somewhere else?
To answer that question, we should look at what caused Moore’s Law in the first place. It was a single innovation, really. Just one idea.
Are FPGAs Harbingers of a New Era?
The title may have put you off. In fact, it probably should have. After all, most of us in the press/analyst community have - at one time or another during the past decade or two - been walking around like idiots wearing sandwich signs saying, “The End is Nigh!” And, we got just about as much attention as we deserved. “Yawn, very interesting, press and analysts, and now back to planning the next process node…”
It gets worse. Predicting that Moore’s Law will end is pretty much a no-brainer. It’s about as controversial as predicting that a person will die… someday. There is obviously some point at which the laws of physics and the reality of economics will no longer allow us to double the amount of stuff we put on a single chip every two years. The question is - when will we reach that point, and how will we know we are there?
What’s Coming When?
As we continue to try (and succeed at) stuffing more circuity into a tiny space than physics allows without great cleverness, we are drifting more and more into the use of multiple patterning. We’ve looked at this a number of times, starting with the simplistic view of litho-etch-litho-etch (LELE) approach and then digging deep into the far less intuitive self-aligned (or spacer-assisted) double-patterning (SADP).
As we’ve mentioned here and there, these technologies are, to some extent, in production – and more is coming. What’s a bit confusing is what’s coming when and why. Today’s musings attempt to sort that out.
But before we do that, let’s do a quick review (with more details available in the prior pieces linked above). Multiple patterning is a trick we play so that we can place features closer together than can be done with a single exposure. The solution? Split the mask pattern in half and do two exposures.
Education Meets High Tech
This week Fish Fry is all about technological innovation in education. From kindergarten to college, from Malaysia to Texas, we look into recent technological advances that aim to even the educational playing field in the United States and across the globe. My first guest is Scott McDonald (Rorke Global Solutions). Scott unveils Rorke’s new digital learning system and discusses with me how Rorke was motivated to break ground on this high tech education revolution. (We also throw in some basketball trash talk.) Keeping with our education theme, Silicon Cloud International CEO Mojy Chian joins Fish Fry to explore the future of cloud computing and how Silicon Cloud International's educational cloud centers hope to create a whole new generation of chip designers.
Cadence Rolls New Protium Platform
System on Chip (SoC) design today is an incredibly complicated collaborative endeavor. By applying the label “System” to the chips we design, we enter a realm of complex, interdisciplinary interactions that span realms like analog, digital, communications, semiconductor process, and - with increasing dominance - software. Since the first SoCs rolled out a mere decade or so ago, the composition of design teams has shifted notably, with the percentage of cubicles occupied by software developers increasing much more rapidly than those of any of the other engineering disciplines. In most SoC projects today, software development is the critical path, and the other components of the project are merely speed bumps in the software development spiral.