DAC in the Saddle Again

Food Trucks, Art Shows, and Design Automation

by Amelia Dalton

What do algorithmic art, food truck fare, and EDA software have in common? This year's Design Automation Conference! In this week's Fish Fry, we get a special sneak peek into the year's biggest EDA event with DAC Chairman Chuck Alpert. Chucks gives us the lowdown on all of the coolest events at the expo this year (Austin food trucks on the show floor?!), the details of the inaugural DAC art show and super cool keynotes (soccer playing robots?!), and much more. Also this week, we take a closer look at how a unique collaboration between Posterscope and NBS is hoping to stop mosquitoes dead in their tracks - one billboard at a time.

 

Industry Trends: Ecosystems and Packaging

Device Packaging May be Going to the Ball

by Dick Selwood

Two weeks after the three-ring circus that was embedded world (see "Embedded World Diary"), I was at another event: SEMI's ISS Europe. This was on a different scale and had a different topic. SEMI is the trade body for the companies that build the kit and supply the materials that, in turn, are used to make micro- and nano-electronics. ISS Europe (Industry Strategy Symposium) is a two-day event where members of SEMI are briefed on the trends that are going to shape the industry.

Now some of these trends, particularly the big global socio-economic issues, such as the overall economic climate and the important role of China, were discussed in “May You Live in Interesting Times".

 

Designing for Directed Self-Assembly

Yeah, There Are Rules. (And Tools.)

by Bryon Moyer

There’s going to be a new kid in town when we get to 5 nm. Her initials are DSA. And she’s not going to be completely transparent to designers, although tools will likely help to minimize the impact.

We’re talking about directed self-assembly (the D, S, and A in DSA). Which we’ve talked about before – it’s been one of our reliable post-SPIE-Advanced-Litho-conference update topics (whether fundamentals, EDA impact, the impact on how masks relate to actual patterns, or just the latest). And it will be an option, as I suggested, at the 5-nm node (with ongoing 7-nm work to bring it up).

At this year’s SPIE Advanced Litho, Imec’s Roel Gronheit made an update presentation and alluded to the notion of “DSA-friendly design.” That caught my attention, and, in a quick conversation afterwards, he directed me to Mentor Graphics’ Andres Torres, who has been heavily involved in much of the leading DSA work. So I was able to sit down with Andres later and discuss just what it means for a design to be DSA-friendly.

 

Mentor and Verification Productivity

Recent Emulation and VIP News

by Bryon Moyer

Tired of spending all that time doing verification? Yeah, well, everyone is, so get in line for the “Can I Finally Be Done Verifying - PLEEEEZ??” window, where you can submit your coverage numbers and see whether you get a weekend or you get sent back to the lab for more verification.

Verification productivity has always been a hot topic, ever since it was figured out that you guys spend about 70% of your silicon efforts on making sure that the other 30% was done correctly. Mentor Graphics recently made a couple of announcements intended to provide some relief for the poor verifiers that desperately need to get home for a shower and some sleep.

 

Integrity Simplified

Mentor Upgrades HyperLynx

by Kevin Morris

These days, the metal on your PCB has to do a lot more than just connect a few dots. With the pervasiveness of high-speed serial interfaces and other signals that put a premium on signal integrity (SI), most board designs can’t get away with simple-minded placement and routing anymore. And, with the compression and perforation of power planes, we can’t take power integrity (PI) for granted either.

The situation is only getting worse. New protocols and standards for high-speed interfaces like DDR4, multi-gigabit Ethernet, and PCI Express put even more strain on the design, and continually increasing operating speeds combined with decreased voltages up the ante yet again. It is becoming rare for a design team to be successful with a leading-edge PCB without state-of-the art SI and PI simulation and analysis.

 

Math Works Harder

MATLAB Upgrades Boost Design Creation

by Kevin Morris

“Verilog and VHDL are the most natural and efficient ways for me to express my design intent.”
— No one. Ever.

Whether we’re doing FPGA or ASIC design, or programming the latest DSP, most of us don’t start out our project with regular hardware description languages. In fact, if we’re developing or tuning an algorithm, or if we’re somehow applying math to our problem, a great many of us do the early work in MATLAB. It makes sense. For translating mathematical ideas into specific algorithms, and verifying the performance of those algorithms on early data sets, MATLAB is worlds more productive than jumping straight into the design of hardware, or even into C/C++ coding.

 

More Compression, Less Area

Next-Generation DfT in Cadence’s Modus

by Bryon Moyer

If you’ve ever digitized your vinyl albums, you know that you have a decision to make: what format should be used to store the music? There are lossless formats like wav and flac, but they take a lot more space. Mp3 is much friendlier to your small, limited-memory listening gadget, but you lose something in the translation. It’s lossy, so the space savings come at a price. Whaddaya gonna do?

Turns out that there’s a similar problem with chip test circuits. It’s not the only problem, but compression-vs.-loss is an issue that Cadence claims to have, well, not solved (it’s never completely solved until it’s lossless and small), but improved. As a result, they’ve announced a new Modus tool for this new approach to chip testing. (Yes, another tool name ending with “-us.” I just hope they don’t do a tool that flattens out hierarchy…)

 

Synopsys and SPICE Go Native

An Environment of Their Own

by Bryon Moyer

Want to feel old?

Wait… hello? You still there?

OK, whew… I thought you’d already answered, “No” and moved on to something else. Guess I should vet my questions more carefully.

Here’s the deal: HSPICE is 35 years old. I know… I probably should have given you time to pour a drink. I mean… I was running SPICE before there was an HSPICE. (Barely…)

(Takes a few gentle rocks in the chair…)

 

Prove It!

The New Era of Design Verification

by Amelia Dalton

Can you imagine a world without mistakes? Maybe it would be cool, but most likely it would be pretty boring. Heck, it might even mean some of us would lose our jobs. This week’s Fish Fry, we visit a conference dedicated to engineering mistakes: DVCon. We investigate three major the themes of this year’s Design Verification Conference: UVM, emulation, and FPGA-based prototyping. Shishpal Rawat (Chairman - Accellera Systems Initiative) and I sit down to discuss the importance of standardization in emulation and UVM, the value of design verification tutorials, and why verification needs to happen at many different levels of abstraction. Also this week, we check out the advantages of an integrated prototyping solution which may just put ad-hoc FPGA-based physical prototyping out of business once and for all.

 

A Unified Chip/Package/Board Flow

ANSYS Brings Mechanical and Electrical Together

by Bryon Moyer

ANSYS has recently released version 17 of their tools, simply referred to as ANSYS 17. The improvements they made cover a lot of ground, much of it having to do with mechanical design. Which might lead you to think, “oh, this is a mechanical tool; I can move on, since it’s not for me.” But be not so hasty: we’ll return to this in a minute.

Their theme for the release is 10x, meaning lots of things are 10x better. 10x is a convenient number (I personally think of it as a convenient threshold for how much better something needs to be to get a user to switch from something else). Again, this distributes over so many feature changes (many of them mechanical) that we could take all day chasing that angle. But suffice it to say that many of the changes aim to smooth or unify flows and, in general, save time and effort.

 

FPGA Synthesis Showdown

The Big Game that Never Ends

by Kevin Morris

I’ll be the first to admit that I don’t understand cricket, but I’m told that cricket matches can sometimes run for days on end, and that it’s often unclear who’s winning until, suddenly and unexpectedly, one team meets some arbitrary victory conditions and then goes home to celebrate with a few pints. The FPGA synthesis game is a lot like that. It’s a high-stakes game with vast amounts of revenue at stake, not to mention some serious technology bragging rights, but it’s never really clear who’s ahead, who’s behind, or even what the rules were in the first place. It’s been going on that way for something like twenty years, and despite fierce competition and incredible technological advances in the tools, the scoreboard is still basically a bunch of gibberish. Nonetheless, the audience is stuck on the edge of their seats (Maybe they’ve been Super Glued there?) watching every move in this weird and wacky contest between tool nerds that have never met.

 

A Non-FinFET Path to 10 nm

GlobalFoundries’ FD-SOI Alternative

by Bryon Moyer

It was the coolest transistor development in many a year. Rather than continually squishing transistor parts closer and closer together, we flipped it to vertical and celebrated the arrival of the FinFET.

Which was great: it gave us a way to keep increasing performance in many of the applications where the value lies in the speed of the circuit. But after the initial party was over and we started picking up the pointy party hats and nursing the hangovers with massive doses of ibuprofen, we started looking at the bill. FinFET is nice, but it’s also expensive. And, while we’re throwing stones, it’s also not so great for analog and RF designers based on the quantized nature of the gate. You can’t increase channel dimensions by 1.5 times; it’s either 1 or 2.

 

The Business of the Impossible

ASML’s EUV Lithography Tools Push the Boundaries of Invisible

by Jim Turley

There aren’t many industries where 15 units qualifies as “a big order.”

Battleships. Nuclear power plants. And EUV tools.

For the 14,000 employees at Dutch lithography company ASML, 15 orders for EUV tools is a big deal. Even though that number spans five years and four generations of the company’s EUV equipment, it’s still considered “volume.” Walmart they ain’t.

EUV (extreme ultraviolet) lithography is still is bit space-age and sci-fi for many chipmakers. We’ve been shining DUV (deep ultraviolet) light on our chips for quite a while now, but the limits of that technology are making themselves known.

 

EDA: Expanding or Fading?

The Nature of a Bursty Business

by Bryon Moyer

Those of you who have been with us a long time may well remember that our humble journal didn’t start out as EE Journal. In fact, it started as FPGA Journal, with founder Kevin Morris as chief editor, writer, cook, and bottle washer. A few years later, we added a new Embedded Technology Journal (whose current embodiment is ably managed by Jim Turley). Only several years after that did we take on IC design specifically, which is when yours truly joined the fray.

And then we opened our umbrella wider, covered more topics, and consolidated into a single EE Journal, with a number of specialized “channels” that would allow our readers to on their specific areas of interest. Out of the IC newsletter were born two channels: EDA (for the tools) and Semiconductor (for the underlying silicon technology).

 

High-Level Design for Everyone

Xilinx Rolls Out HLx

by Kevin Morris

For more than two decades, the promise of high-level design methodologies has been dangled in front of digital hardware designers. High-level design was going to revolutionize our design process. It would make us dramatically more productive. It would make us vastly more agile and adaptable as our design requirements evolved. It would make us into Super Engineers - or it would take away our jobs.

Everyone who has designed at the register-transfer level (RTL) using hardware description languages (HDLs) such as VHDL and Verilog knows, deep down in their bones, that RTL is not the answer. The detailed, nit-picky, verbose, cryptic, architecture-specific, technology-locked nature of RTL design is almost incomprehensibly clunky. Yet, for more than twenty years, it has persisted as “the way it’s done” when designing digital hardware.

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