Achronix Beats the Odds

Full Production on High-Performance FPGAs and Tools

by Kevin Morris

Few challenges in the world of high-technology startups are as daunting as that of putting a new FPGA company on the map. Sure, there’s the obvious hurdle of coming up with a better mousetrap - against two extremely innovative and experienced mousetrap makers who most certainly have deeper pockets than you. And deep pockets matter. If you don’t have the resources to deal with the nine-digit-dollar entry fee for new device development at competitive process nodes, you’re better off not leaving the starting line.

Then, there’s the matter of timing the waves. Let’s say you came up with a fancy new FPGA design, and you planned to implement it at 28nm. If you started designing at about the time 28nm technology was first available, and you executed your design project perfectly, you’d at least be on an even playing field with the big established companies. (Not that the even playing field would help that much, given that the other teams have about 50x the number of players you’re fielding.) But chances are, you didn’t execute your design project perfectly, and chances are, the semiconductor fab didn’t give you top priority compared with their long-time high-paying partners. That means you launched your 28nm a year or so later than the big guys.

 

Build Your Own EDA Tool

Without Competing With the Big Guys

by Bryon Moyer

So your company needs to design a system-on-chip (SoC). On the one hand, there’s a lot of that going around. On the other hand, the cost of doing an SoC – especially on an aggressive silicon node – is so expensive that the number of companies that have the cash to do that is decreasing.

Which limits the number of competitors to a certain degree. But you’re still going to have competitors. How are you going to make sure that, when system builders are looking for an SoC, they choose yours?

That’s how a standard product marketing discussion might go, but things can work differently with SoCs, While you might find merchant-market SoCs for, say, a communications protocol like Bluetooth or for power management, many SoCs are created by, or on spec for, system builders, so presumably the feature set has been tuned to be exactly what the system needs. So, really, it’s the system architects that are defining the differentiating aspects of the system, and the SoC is “merely” an implementation of those features.

 

Engineering Childhood’s End

Radio Shack Goes From 50-in-1 to None

by Kevin Morris

My fingers trembled and my heart pounded. I carefully bent spring terminal #35 and inserted the tinned end of the final wire. I was confident that I had double-checked every connection, but I still felt unsure.

Nothing happened.

As I slowly turned the knob labeled “variable condenser,” I thought I heard a hiss or some static. Then, suddenly, Merle Haggard singing “Branded Man” boomed through my tiny earphone. I jumped! I couldn’t believe what I was hearing. I hated country music, and it was the most beautiful sound my seven-year-old ears had ever heard.

 

MathWorks Targets Hardware/Software

Prototyping MATLAB and Simulink Algorithms on Xilinx Zynq and Altera SoCs

by Eric Cigan, FPGA/SoC Technical Marketing, MathWorks

The year 2011 saw a signature development in the FPGA industry – the introduction of two new programmable SoC devices. Xilinx introduced the Zynq-7000 All Programmable SoCs, and Altera introduced the Cyclone V SoC and Arria V SoC FPGAs. These new programmable SoCs, each packing a high-performance dual-core ARM Cortex-A9 MPcore along with ample amounts of programmable logic, offered advantages for a plethora of applications. Now designers could enjoy the benefits of software application development on one of the industry’s most popular processors while gaining the flexibility and throughput potential from hardware acceleration on a high-speed, programmable logic fabric.

 

Get to Market Faster with Modular Circuit Design

by Craig Armenti, Zuken USA, Inc.

The concept of designing, validating and then reusing functional blocks in integrated circuits (ICs) has been entrenched in the electronics industry for decades. Software development has a similar model utilizing libraries of common function calls or objects. However, the concept of reusing printed circuit board (PCB) modules is much less common. Reusing PCB modules for common or commodity functions offers considerable advantages, for example avoiding potential signal integrity or thermal problems, by utilizing circuit data whose performance has been proven in previous generations of products. The key to successful modular circuit design is a data management system that can store and control access to modular reusable blocks, manage information that is critical to design reuse, such as the layer structure of a routed block, and interface easily with the circuit design software. The end result is a reduction in time during schematic capture and PCB design, along with fewer design errors, making it possible to bring quality products to market faster.

 

Verifying Your Awesomeness

The Mire of Modern System Verification

by Kevin Morris

If a clock tree fails in a forest, and there are no vectors to catch it…

Verification has always been the black sheep of the engineering family, and for understandable reasons. Design teams are made up of intelligent, capable, and - dare we say occasionally arrogant - types who don’t take kindly to the notion that their work contains errors. Yet, we have verification teams who make their entire career finding the bugs in the work of designers.

Does this sound like a recipe for peace and harmony?

As system complexity has exploded, design productivity has largely kept pace. There is, of course, the ubiquitous EDA marketing slide - a graph over time showing an expanding “gap” between the number of gates we can design and the number of gates Moore’s Law will allow us to put on a chip.

 

EDA for SETs

A Flavor of Single-Electron Transistor Algorithms

by Bryon Moyer

A few weeks back, we tackled the concept of a single-electron transistor (SET). And we saw how they could be arranged in a hexagonal form for use as a non-volatile programmable fabric. The whole topic originated for me in an ICCAD paper that discussed EDA algorithms for implementing logic in such a device. Well, before discussing that, we needed to introduce SETs. So, having done that, we now return to the originating topic: how do you take random logic and implement it in a SET fabric?

 

2014 Letdown

Have We Lost The "Wow" Factor?

by Dick Selwood

At a recent semi-social, semi-business function, I was asked what I thought the highlights were in electronics in 2014. I was stumped. Not only could I not think of a highlight then, I still can not think of anything that really stuck out in the year.

I've sat through many new product presentations and press briefings and received many more press releases, and there is a lot of creative thinking and very good solid engineering going on, resulting in good solid products that are meeting customer needs. I've written about some of them and hope to write about more some time later in the year. There have also been some things that have been a complete waste of time – but I have been moderately successful in trying to wipe those from my memory.

 

Electronic Design - Yesterday, Today, and Tomorrow

An In-Depth Interview with Kevin Morris

by Amelia Dalton

Time to break out the sparklers, the bailing wire, and your best O-scope. We’re having an EE party In honor of the 50th Anniversary of Moore’s Law. In this week’s Fish Fry, we investigate how Gordon Moore's legendary 1965 article in Electronics Magazine set the stage for a remarkable half-century of innovation in our industry. We also look at how (and why) Moore's Law may not mean as much going forward as it has in the past. My guest is Kevin Morris, editor-in-chief of EE Journal. Kevin is here to chat with me about how the 50th anniversary of Moore’s Law plays into the future of electronic design, his FORTRAN days, the learning curve of FPGA design, and even a little bit about his favorite project of all time.

 

Instruments for the Black-Turtleneck Crowd

Saleae Logic Analyzer is a New Take on Lab Equipment

by Jim Turley

“Oh, and one more thing…”

You can almost hear the ghost of Steve Jobs introducing the Saleae Logic Pro 16, gesturing to a rear-projection screen as he slips the device out of his pocket. It’s that kind of logic analyzer.

Huh, what? Trendy, stylish, desirable test instruments?

Believe it. The Logic Pro 16 is a hardware logic analyzer that even a design aesthete would love. It’s the lab instrument for the SoHo/Noe Valley/Pearl district crowd. And I have one. And no, you can’t borrow it.

 

Lucio on EDA Investment

Kaufmann Award Winner Shares His Thoughts

by Bryon Moyer

So you’ve been toiling away in the depths of the EDA world and you are struck by an idea of monumental brilliance and potential. You drop what you’re doing and go off into a cave for a while to flesh it out to the point where you can solicit a hearty investment by a forward-thinking manager of an aggressive investment fund.

What are your chances?

It certainly won’t come as a surprise that you’ve got more than one roadblock to get by. It’s not an easy investment environment out there – for high tech in general (at least for anything you can actually put your hands on). Even tougher for EDA.

 

What You Call EDA, I Call IP

EDA Past, Present, and Future with Lucio Lanza

by Amelia Dalton

He's toiled at this project for years - dreamt about it, laid awake at night thinking about it, and even built a lab in his basement to test it. Eventually he brought in friends (from work mostly) to fill in the missing pieces, and before he knew it they really had something. We all know this story. It has played out time and time again. It's the story of the startup, and today's Fish Fry celebrates the men and women who work every day with innovation in their hearts and minds. My distinguished guest is Lucio Lanza, an EDA mentor, venture capitalist, and believer in startup innovation. Lucio is here to explain why funding startups is so crucial in today's EE ecosystem and where he thinks EDA is headed in the future. Also this week, we check out a brand new way to get that semiconductor quote you've been looking for without giving you a headache or breaking your fax machine.

 

New Synopsys SoC Test Features

Cell-Aware: Meet Slack-Based. And STAR: Meet eFlash.

by Bryon Moyer

Ah, the air has cooled. The sun lolls about at a low angle for a few tentative hours. Morning frosts seal the fate of any remaining tender plants. Here in northern Oregon, the Gorge winds blow random gale-force patterns, making it unnecessary to sweep the leaves off of the patio. And, slightly farther north, it’s ITC (that would be the International Test Conference) season, in Seattle this year.

Which means it’s the season for test announcements by EDA companies. Synopsys made some noise, but not with one big blockbuster new thing; rather they assembled a couple of newsy bits that, summed together, merit some discussion.

Just to organize my thinking here, so that I don’t get us lost, there are two basic announcements: Cell-aware+Slack-based testing and STAR for eFLASH. The first involves two subtopics that we should review first.

 

Single-Electron Transistors

A Whole New Way of Switching

by Bryon Moyer

I love surprises like this. You go into what promises to be a wonky, even dull, conference presentation – and come out agog.

That’s exactly what happened to me at the recent ICCAD in San Jose. It was a presentation based on a collaboration between the University of Michigan, Shanghai Jiao Tong University, and National Tsing Hua University about some placement or routing algorithm, but it happened to involve a transistor type that I’d never heard of. And… I don’t know, there was something about the regularity of it, perhaps its elegance, illuminated through a very lucid presentation, that caught my fancy. Heck, even with no prior knowledge, I could actually follow most of the talk. That was exciting enough. Great success!

So… what was this thing? It was a way of implementing logic on a fabric of single-electron transistors (SETs). In fact, a reconfigurable fabric. This could be your new FPGA some years hence. But, while I could follow the logic of the presentation, I had no idea what a SET was, nor did I understand why certain constraints existed that affected the algorithms presented.

 

Plan 8 from Outer Space

Calypto’s Catapult 8 Takes Us Higher

by Amelia Dalton

Bob killed the headlights and put the car in park. We sat in silence. Eerie lights danced on the horizon. First east, then west, and then straight up into the night sky. We watched with mouths agape as the lights came closer (and closer), only to quietly fade away. A UFO in our midst? Not quite. HLS. Most of us have been watching the skies in hopes for the arrival of High Level Synthesis for years. Steering today's HLS-powered flying saucer is my guest Mark Milligan (Calypto Design Systems). Mark is here to reveal the mysteries of Catapult 8. He'll shine a light on how HLS is powering image processing and video applications, and explain how we can get to design closure from the top or the bottom. Also this week, we introduce a kickstarter campaign that aims to bring fashion-forward wearable fitness monitors to your next holiday wish list.

subscribe to our eda newsletter


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register