Xilinx Acquires AutoESL
In 1995, I strutted my marketing suit onto the stage at the Design Automation Conference and told the world that a revolution was afoot. I had seen the light - the path to engineering enlightenment, the road to the future of design - and I wanted to share. No longer would designers have to toil and struggle with the arcane anachronisms of register-transfer-level descriptions and clock-accurate timing. Now, thanks to the amazing capabilities of high-level synthesis, thousands of lines of detailed and incomprehensible RTL would be replaced by a few elegant lines of ordinary C or C++, with clear and self-explanatory loops and conditionals, that would magically be transformed and re-transformed into whatever hardware
There’s a battle shaping up as yet another entrant into the assertion synthesis field makes some noise this week.
We’ve kept an eye on assertion synthesis over the last year or so. Tools and methodology vendors lament that assertion-based verification has been slow to catch on. Some say that’s because it’s too hard to generate and work with assertions. Hence tools to make that easier.
Last summer we reported on NextOp’s entry into the fray. We also noted that their approach was qualitatively different from that of another player, Zocalo, in that Zocalo enables assertion synthesis before the design is done; NextOp generates assertions from RTL already written.
Fish Fry - January 28, 2011
In Fish Fry this week, Amelia delves into sneaky ways to take advantage of the variance found in our semiconductor processes, checks out the variety of features found in the new family of 28nm FPGAs from Altera and discovers a truly unique USB hub from Thanko. Also this week, she looks forward to next week’s DesignCon and announces a winner of last week’s nerdy giveaway.
When I was younger, I briefly became very interested in collecting trading cards – primarily baseball cards. It was always exciting to sort through my weekly pack. However, as time passed and my pile of cards grew, it became more difficult to find the ones that I needed to help fill out my collection. As a kid I was frustrated by what I thought was bad luck. Now years later I understand the math that made that frustration inevitable. It’s the same math that can lead to stymied attempts to achieve functional coverage closure in design verification using random stimulus generation.
Revealing Secrets Buried Deep Within Your Silicon
A well-worn literary device in any self-respecting bedtime story ensures us that, no matter how evil the villain, there’s a hidden speck of virtue whereby he or she can achieve redemption.
OK, so I’m not going to go so far as to ascribe literary qualities to these pages, lest credibility be forever lost. But we’re going to take one of the up-and-coming anti-heroes of our time and expose the surprising goodness lurking within.
And who might this beneficent ne’er-do-well be? That infamous processing bugaboo, variation.
Silicon fabrication, like all manufacturing, is about applying order to things. Remaking the world according to our specifications. Entropy is the enemy.
Except when it isn’t.
Fish Fry - January 21, 2011
In Fish Fry this week, Amelia introduces the fabulousness of the new EE Journal, checks out the new microcontroller-multi-core combo pack from NXP, and tries to sort out the future of chip manufacturing. Also this week, She interviews Kozio co-founder Joe Skazinski, announces a brand new super cool nerdy giveaway and referees a Robot Haiku Smackdown....and here’s a tip, keep listening until the very end...
It used to be that real men had fabs. The small number of companies designing chips also developed their own processes and built fabs for only a few tens of millions of dollars. If they had spare capacity they might also run other peoples’ designs through the fab. The fab price tag got bigger as processes chased Moore’s Law, the industry went through cycles of growth and contraction, and lots more people wanted to make chips. So companies were set up just to make chips. These are the foundries.
Fish Fry - January 14, 2011
In Fish Fry this week, Amelia examines the new ARM/Microsoft announcement, the squishy ownership of IP in today's electronic design and how the Verizon iPhone plan will affect smartphone users in the U.S.
You down with OPC?
Ownership is a big thing for an engineer. When you’re done with a project, you can stand back and state proudly, “I made that!”
Well, it used to be that simple. Perhaps now it’s more like, “See your TV? Well, it needs backlights to work and those backlights are divided into zones and something has to decide how to light the zones to keep power usage down and there’s a big chip that controls a lot of this stuff and a portion of the chip handles the zones and that portion has to talk to the rest of the chip over a complex interface, and that interface is really really important for the picture to look good. So, that interface? I made that! OK, I didn’t actually make it, but I designed it!”
Ownership is good. If you’re going to put your name on it, you want to make sure it’s going to be good. Stated conversely, if you want it done right, do it yourself.
Synthesis and Place and Route Hold Keys to the Kingdom
I got a note a few weeks ago from an engineering student: “Why does it take so long to compile my FPGA design?” This twitter-esque brevity led me to semi-consciously fire off some half-helpful standard response, to which the student replied: “My other projects... seem to compile almost immediately, but the FPGA takes forever.” A layer of the onion had peeled back. This was a student who was approaching HDL as just another programming language. To him, the step of synthesis-and-place-and-route was just another “compiler,” and he couldn’t understand why this compiler took so much longer to do its work than, say, gcc.
“Freedom!” — Mel Gibson, Braveheart
Freedom is a good thing, right? Whether it’s political, design, or economic freedom, we generally believe that more freedom—more flexibility to make choices—is unequivocally a good thing to have. You can never have too much freedom.
But is that really true, even for design engineers? At the far end of the political spectrum, extreme freedom is called anarchy: the complete absence of control. And most people use the word anarchy in a bad sense, so maybe there is such a thing as too much freedom. Total economic freedom, such as the type Ayn Rand espoused, also tends to divide opinions. Some see it as the triumph of personal will and responsibility, while others view it as economic oppression. Entire governments have been formed (and toppled) on such questions.
“So why do you think you’re right for this job?
“Well, it’s pretty much exactly what I’ve done for the last 10 years. We were almost done with something just like what you’re about to develop when the economy tanked and the project got canceled.”
“Hmmm… OK, which defrumpitation algorithm did you use?”
“Well, we started with the FTL-25 open-source algorithm…”
“OK, good, that’s what we’re using…”
“… yeah, but we found that performance was horrible – it’s really inefficiently put together. We pretty much had to develop a new one from scratch. It took a lot of tries to get it just right – it’s not obvious – but we managed it. We were going to publish the results, but it all got packed up before we had a chance to.”
What Is the Key?
[Editor’s note: Atrenta’s Ron Craig and Magma’s Bob Smith got together to provide two viewpoints on what is going to be most important for timing closure in 2011. What follow are their thoughts.]
What is timing closure in the 2011 SoC design environment? Ron Craig, Senior Marketing Manager, Atrenta Inc.
Backend timing closure is an incredibly inefficient process, fraught with uncertainty. In an ideal world, an engineer would need to run a single pass through the synthesis to GDSII flow and he'd be done. But the reality isn't that simple. I've heard stories from well-known companies of up to 20 backend iterations to close timing, with each iteration taking up to a week. Evidence such as this would suggest that timing closure in the backend is no longer working – that this “tortoise” will indeed eventually get there, but at what cost? Is there a way to add certainty to the process?
Engineers of a certain age will remember when Mentor Graphics made engineering workstations. Remember those? They were overpriced computers with big monitors that every self-respecting hardware or software designer had on his/her desk, as opposed to a Windows or Macintosh machine that marked you as a receptionist, or worse, a marketing dweeb.
Mentor was just one of many companies making engineering workstations, including Apollo, Daisy, Intergraph, and Sun Microsystems. Remember them? Unlike most of its competitors, however, Mentor Graphics survived. Flourished, even. Mentor is now a big embedded-development company with all kinds of spiffy technology to help hardware and software designers.
Altium Leads Another Design Tool Revolution
Nick Martin, the founder of EDA’s most unconventional company, Altium, Ltd., is not afraid of being different. Since 1985 when the company (formerly known as Protel) released its first EDA tool, Nick and his growing band of nerdy rebels have been challenging the status quo in electronic design automation. The company has always had the philosophy of giving the individual engineer the tools he or she needs to get their job done, without the barriers of cost and access posed by traditional EDA.
Nick’s vision has always extended beyond the here and now. The self-appointed vanguard of the constantly moving target of innovation has capitalized on the company’s unique circumstances and culture to produce products and services that track dangerously close to that bleeding-edge of engineering design - where the concepts embodied by the design tool flow are just a little ahead of the mainstream engineering crowd, but well within view of forward-thinking designers.