The Mathworks Simplifies Transfers
A few years ago I took the train from San Diego back home to Sunnyvale. This actually involved three steps: a commuter train to LA, Amtrak to San Jose, and then a commuter train to Sunnyvale.
The train is a fabulous way to travel. However, it is also true that Amtrak is fabulous as long as you don’t have to be anywhere at any particular time. And, true to form, we stayed stationary in San Luis Obispo for a couple hours while they sorted out some crew problem.
I had planned the trip with lots of margin for error. But not quite enough. We arrived into San Jose six minutes after the last commuter train of the day left.
I even asked a conductor ahead of time to see if any arrangements (or acceleration) might be possible to make the connection.
Traditionally, simulation-based dynamic verification techniques — think directed tests, constrained-random simulation and the like — have collectively been the workhorse of functional verification. But it's fair to say that this horse is straining under the load and in need of some relief. The source of this strain: increasing SoC integration and overall complexity. This, in turn, drives up verification costs. Software licenses, hardware servers and staff to set up and run regression environments all cost real money, which of course remains scarce given the tepid economy. Even with unlimited resources, due to that increasing design complexity, more and more code remains effectively beyond the reach of simulation.
Luckily relief is available in the form of various static verification techniques. One such technique is formal verification, a systematic process of ensuring, through exhaustive algorithmic techniques, that a design implementation satisfies initial requirements and specs . Instead of stimulating the design to observe its behavior, formal verification relies on heavy doses of math to analyze all possible executions. Formal verification often works well with assertion-based verification . Once a specific behavior is captured with a property language such as PSL or SVA, formal verification can be used to crawl even into the darkest nooks and crannies of the code.
ModLyng Reinforces an Old Paradigm – With a Twist
We’ve noted here before how old-school analog designers are. While digital designers have moved up in abstraction layer by layer by layer, analog designers still do things the old way. They still draw schematics. They still push polygons. OK, they don’t cut rubylith anymore, but that’s about it.
That’s not to say that they’re stuck in the past; it’s just that no one has really given them a better alternative – or at least not one that’s natural and easy to use. So they’ve remained in their own world with their own tools and their own methods, largely owned by Cadence – conceded by all to be the master of analog.
Actually, no one seems to call it analog. It’s called “custom.” Seems like you could have custom digital circuits as well, but never mind. In this world, “custom” is synonymous with “analog.” Simply put, they’re the only ones that are going to concern themselves with the exact location and shape of each transistor.
“Things would be so much easier if I just knew what you wanted!”
A statement that may strike fear into the heart of many a spouse, this simple plea calls for something other than just charging ahead. It suggests a negotiated path as a better way. It suggests the opening of dialog.
Ironically, as hard as this can be for humans to achieve, it has become more and more common amongst our inanimate brethren. All the way back to the negotiation of baud rate between faxes (the original, “Can you hear me now?”), we have imbued machines with the ability to negotiate the terms of their operation.
Often the benefit of this is backwards compatibility, where newer machines may need to co-operate with older ones, and they have to figure out their highest common denominator. Or, when machines need to work together, but where various features are optional, they may need to declare which of the optional features have been implemented.
Or, Will The Real Standards Effort Please Stand Up
It seemed pretty straightforward based on the press release headline: “Synopsys and IEEE-ISTO launch industry body to evolve Interconnect Modeling Standard.”
Always interested in filling yet another in my seemingly endless supply of pockets of ignorance, I made a couple phone calls to understand a bit more about what was being standardized.
And in so doing, I waded into something of a minor hornet’s nest. Actually, that’s a bad metaphor, because, had I done that, I would have been badly stung. As it is, I sit here, more or less no worse for the wear, as the stinging goes on around me.
Is this some huge sleeper issue that’s going to dominate the headlines with salacious, bitter, biting comment and counter-comment? Alas, no, probably not. But it does shed some light on the sometimes-murky world of standards-setting. And, more specifically, on when a standard is a Standard and when it isn’t.
Once upon a time, and a long time ago it was, a company in what was struggling to be known as Silicon Valley (Germanium Gulch never really caught on) had an order for a discontinued product. The customer was pressing, so the company ran a batch of wafers (probably one-inch wafers), but none of the end product worked. A second batch was also DoA. After a great deal of head-scratching, someone remembered that since the last successful production run, clean room staff had started wearing gloves. A third batch went through the line without gloves, and there was enough working product to meet the customer’s needs. One possible explanation was that sodium chloride emitted by the operators’ hands (even though wafers were handled with tweezers) created just enough doping at some stage to tip the process into yielding.
In those days, process development was one part technology and several parts black art. Things are different today, of course. But, if Future Horizons’ CTO, Mike Bryant, is correct, we may be going into even more weird realms of the unknown anytime soon.
As IC design teams adopt advanced process nodes, they are packing more functionality and performance into silicon. However, design challenges are growing as designers push the limits of performance, complexity, size, power reduction, and manufacturing scaling. Starting at 45/40 nm, the increasing complexity of DRC and DFM rules began to stress traditional physical design flows. This trend is expected to continue and worsen at the 32/22-nm nodes, where manufacturing closure may become a serious bottleneck in design schedules. Designers need a new generation of physical design tools to effectively address these issues.
Sources of DRC/DFM Closure Problems
The fundamental source of the recent DRC/DFM closure problem is the continued use of 193-nm light lithography to etch ever-smaller features. To maintain yield, IDMs and foundries are being forced to tighten up their design rules to ensure that physical features that are susceptible to these effects are not introduced into the design (Figure 1).
ASIC Analytic Looks for Anomalies in the EDIF File
“Somethin’ just ain’t right about that boy.”
She snuck a sideways glance at him sitting alone at the counter, nursing a cup of coffee, rumpled like he just woke up in those clothes, oblivious to the furtive comments of those sizing him up at the nearby table. “Yep, I cain’t quite put my finger on it,” she continued, “but he ain’t from this county, that’s for sure. He don’t look folk in the eye, he pert near run me down on the sidewalk th’other day not watchin’ where he was a’goin’. He don’t seem to have a job or nuthin. Just ain’t right in the head, I’m thinkin’.”
“Oh, come on Mae, you’re always getting’ all suspicious and such about new folk. What’s he done to hurt you?”
MethodICs Introduces ProjectIC for Enterprise Project Data Management
So you’re doing a design of this clever, dashy little inner-city small-but-fast car. And, like everyone else, you’re not doing it all 100% by yourself. You’ve invented the wheel enough times to where the thrill is pretty much gone; you’re going to buy some wheels instead and focus your efforts, maybe, on infotainment instead. You know, nothing takes the boredom out of downtown traffic like a video and the ability to update your Facebook page with one hand while you drive with the other and talk on your phone with the other.
And there’s plenty of other stuff you don’t want to redo yet again. So you unearth some of your old moldy dashboard designs. And you pull in some reclining seat IP. And you buy some rear-view-mirror verification models. And there’s this project that someone else at your company did last year where they came up with a high-performance wheel that was really awesome, so you re-use that (after the guy managed to dig up the old design files).
Vennsa Tries to Figure Out Who Screwed Up
Several years ago, while renting a vehicle for an event I was going to attend, the rental guy pointed out that my driver’s license had expired a couple months prior. So he couldn’t rent me the vehicle. My wife at the time bailed me out, but I decided to postpone my departure by a day to avoid the risk of getting pulled over with no license to show. Which meant an emergency trip to the DMV.
I found that I could get licensed quickly, but I had to take the written test in order to do so – something I hadn’t taken (or studied for) since I was a teenager. So, with no preparation, I went off and answered the questions, knowing that these tests have a history of being flaky, and nervous that my ability to drive legally lay in the balance.
I don’t remember what the numbers are, but you aren’t allowed to miss many. And I missed one too many. And I asked about the questions, and there was one in particular that stood out:
Docea Makes the Peace
In the defender’s corner, wearing the blue trunks, with several years of evolution under its belt, scoring knockouts against low-level transistor power simulation and having captured RTL level simulation, with an eye on raising the level of abstraction to TLM and above, reading in UPF and CPF formats, displaying a wide range of views and analyses, the new rising star in a league that’s been dominated by performance, the current champion, going with the flow, fighting the powers that be, Powerrrrrrrrrrrr Simulatioooooooooon!
And in the challenger’s corner, wearing the red trunks, just arrived from the mechanical world, displaying its might with full finite element analysis as well as lightweight prowess for standardized packages, putting packaging to the test, taking center stage in 3D chips, highlighting who’s hot and who’s not, showing the glow as it goes, providing the “hot” in the hot spot, beating the heat in the hot seat, Thermaaaaaaaal Simulatioooooon!
Exactly ten years ago I was helping Adaptive Silicon, a start-up, with their European marketing. The company had a great pedigree, with roots in National Semiconductor and financial and process support from LSI Logic and financial and tools support from Synplicity. (For new readers - LSI Logic is now LSI Corporation and is no longer an ASIC company, as it was then. Synplicity was an independent company supplying EDA tools for FPGAs and is now part of Synopsys.)
The product was an FPGA technology for integration into ASICs and SoCs. The idea was that, within the design, small blocks of FPGA fabric would provide significant flexibility. For example, by adding programmability, it should be possible to fine-tune the design without a re-spin. The same properties would allow a basic design to be programmed to make different members of the same family by changing features in the FPGA area. One use that was particularly attractive was for a product being developed to meet a standard that was not yet finalised: the logic for the standard could be implemented in the FPGA and then field-upgraded when the standard was ratified.
It better be fast.
Whatever it is, whatever it does, it’s all good as long as it’s fast.
We live for speed in our supercharged world. After all, we’ve gone from a society that used to survive on one breadwinner per family to a society with two breadwinners as the norm to the point where some people have to have multiple jobs just so they don’t fall behind. (Well, in the US, anyway.) So we’re busy. Very busy. And we have to toss Facebook updates and tweets in on top of that.
So we have to be able to do things fast.
And your boss promised something impossible to his boss who promised something even less possible to his boss and so on up to the CEO who promised something ridiculous to the Board so that the share price could hopefully go way up for at least a few days and make them a boatload of money. So it’s your responsibility to figure out how to make the impossible, nay, the ridiculous, happen. Now. You’re going to be a busy dude and it’s your fault if it doesn’t happen on time.
Cutting corners never seemed like cutting corners before. It seemed like a practical way to handle real-world problems. You don’t want to make any problem more complex than it needs to be or it will be hard to solve on an everyday basis. So you simplify.
But if the world gets more complicated, then what were once practical simplifications now look like cutting corners, and it’s no longer acceptable.
And so it goes with RC extraction tools. You just can’t ignore the things you used to be able to ignore. This sleepy little corner of EDA has historically drifted quietly along in the shadows, but, more recently, has made some moves towards the spotlight.
And for good reason. The crazy geometries being built in foundries result in all kinds of interactions that never used to occur (or matter). So the simple rule-based approaches of yesteryear are quickly giving way to sophisticated mathematical juggernauts; the question is, how do you balance accuracy against the amount of time it takes to calculate?
From Vertical to Horizontal to Vertical
Axiom 1: No matter what we’re doing, something else seems like a better idea. In many cases this takes us forward in a circuitous semi-linear manner towards something new. We may get there by precise navigation, or, more typically, we arrive in a Brownian random-walk kind of mode – after which we can claim credit for great prescience.
Axiom 2: We have short memories. We look forward, not backward. No wasting time on “been there, done that” when we can focus on “wanna go there, wanna do that.” (Or more succinctly expressed in the modern vernacular simply as “Want!”)
Axiom 3: One leg is shorter than the other. This means that, without suitable points of reference, we tend to walk in circles.