Rockin' and Rollin' EE Style

Vennsa’s Debug Technology and Fish Fry Secrets Revealed

by Amelia Dalton

In this week’s Fish Fry, I interview Andreas Veneris (CEO - Vennsa Technologies) and Sean Safarpour (CTO - Vennsa Technologies) about the history of debug and how exactly Vennsa fits into the big picture of design automation. I also investigate how the University of California Riverside is looking to re-invent electronic computation, and I reveal five things you may not know about Fish Fry. I also have another gift certificate to give out this week, but you'll have to listen to find out how you can win.


Off Script

Springsoft Provides Access to More Data

by Bryon Moyer

At times it’s seemed a sotto-voce religious war.

One side says that a clean user interface aids productivity. The other side says that, well, quite frankly, a graphic user interface (GUI) is a toy, not meant for serious work.

One side says that command-line work is the only real way to do things; the other makes the accusation of engineers trying to keep things obscure and difficult as a form of job security.


What the Heck is FEC?

Focused Expression Coverage Explained

by Ray Salemi

When you think about it, simulating your FPGA is a lot like exercising on a treadmill. You do both of them because you want to avoid bad consequences. Some people seem to like doing it, though you might not see it that way. And you may or may not yet have seen the positive consequences in your life.

In both the case of the treadmill and of FPGA simulation, the biggest question in your mind is "When can I stop?" This is a tougher question for simulation because you don't have a sadistic trainer who makes you keep going.


What “Is” Is

Terms May Not Mean What You Think They Mean

by Bryon Moyer

We’ve created a special domain for legal issues in this country. If it looks like a lawyer might have to get involved, the rest of us steer clear and know better than to try to make sense of things. Even if we understand the words, we might not understand what they mean when they’re used together in a paragraph or document. And, even if we do, it still might not make sense.

But we don’t seem to mind: whatever… leave it to the lawyers. As long as they’re happy…


A Bear, a Transistor and a Process Node Walk Into a Bar

by Amelia Dalton

In this week's Fish Fry, I interview James Wang (SmartBear Software - Vice President) about the age old gap between hardware and software designers and how SmartBear's tool suite can help bridge that divide. Also this week, I check in on Samsung's progress on 20nm process node and investigate how the National Science Foundation is trying to make the transistor obsolete. I have a DE0-Nano Development Board to give out this week, but you'll have to listen to find out how you can win.


(un)Rolling with the Times

by Brad Dixon and Anil Khanna, Mentor Graphics

A HW engineer and an embedded SW developer, who are slated to work together on a common project, strike up a conversation at the proverbial water cooler.

HW guy: “I just finished a month long evaluation for a new co-verification tool. We finally made a decision on the product and vendor we’re going with.”

SW guy (nonchalantly): “Really? I wouldn’t know much about evaluations, I build my own toolchain.”


When Programmers Rule the World

The Talent Pool Determines the Design

by Jim Turley

“Their talents did not quite run to scholarship.”

This was Susanna Clarke’s polite way of describing a pack of idiots. Or more charitably, people who were perhaps in over their heads. Swimming out of their depth, one might say.

We’ve all encountered this type of person at work. Conveniently, they often wear neckties so that we can spot them from a long way off. But even credentialed engineers can wade in over their heads, meddling in technical areas where their aptitude does not entirely correlate with their ambition.


All You Can Eat: A Bountiful Buffet of EE

Ivo Bolsens Talks Programmable Platforms, Kilopass v. Sidense, and The World's Smallest Motor

by Amelia Dalton

In this week's Fish Fry, I've got a bountiful buffet of EE beauty for you to sink your teeth into. I interview Ivo Bolsens (CTO and Senior Vice President - Xiinx) about the changing nature of FPGA design wins and why Xilinx is banking on its Zynq platform to transform the industry as we know it.

Also this week, I check in on the recent rounds of litigation between non-volatile memory IP suppliers Sidense and Kilopass and I dig into the details of the world's smallest motor.

I have a Spartan-6 LX9 Microboard to give out, but you'll have to listen to find out how to win.


Cell-Aware Fault Models for IC Production Test Outperform Gate-Exhaustive Fault Models

by Friedrich Hapke (Mentor Graphics) and Stefan Eichenberger (NXP)

Physical defects within ICs, such as shorts and opens, can occur during manufacturing at any step along the fabrication process because of the complexity of modern CMOS technology nodes. The conventional approach to test for these physical defects includes structural tests using classical fault models such as stuck-at (SA), bridging [1,2], and transition faults [3]. This approach has efficiently addressed defects between standard cells and defects at input and output ports of library cells.


A Sweetener for Research Labs

Rhomap Tries to Simplify Magneto-Transport Measurement

by Bryon Moyer

For many people, the arrival of the fall holiday season means that treats are on the way. And, for that extra bit of fun and “I made this myself” pride, there’s nothing like making candies and fudges and other confections at home.

But working with sugar can’t be taken lightly. In order to get good, consistent results, it takes a steady hand and – most importantly – good temperature control.


More Adventures in EDA Land

Atrenta's SoC Realization and Han Solo in Ice

by Amelia Dalton

In this week's Fish Fry, I interview Mike Gianfagna (Vice President of Marketing - Atrenta) about Atrenta's role in reshaping the EDA industry, how front-end design has changed recently, and how SoC Realization fits into the EDA ecosystem.

Also this week, I look into a fantastic new gift that might just be perfect for that nerdy someone in your life.

I have a brand new nerdy giveaway to give out, but you'll have to listen to find out how to win.


A Maze of Twisty Little Passages

An Attempt at Understanding the Basics of DO-254

by Bryon Moyer

We recently invoked the fear of slipshod software programming as we attempted to slog through the maze of safety-critical standards facing software engineers.

But guess what: programmers aren’t the only ones capable of turning out shoddy goods. Hardware engineers can, also. But, unlike the software world, the focus in the hardware world seems to be more squarely on one standard: DO-254.

DO-254 appears to have much in common (other than origin) with DO-178. So much so, in fact, that I found a DO-254 blog site with FAQs that appeared to be copied verbatim from a set of DO-178 FAQs, with a sloppy job of search-and-replace that left such odd statements as “avionics systems are comprised of both hardware and hardware.”


Magma Rising

How Rajeev Madhavan is Taking Magma to the Next Level

by Amelia Dalton

In this week's Fish Fry, Amelia interviews Rajeev Madhavan (Magma CEO) about Magma’s Silicon One initiative, how he thinks Magma fits into the EDA ecosystem and where EDA should be headed in the future. Also, Mentor Graphics plays musical product lines and Catapult C finds itself with a another company. Amelia gives some wild speculation on what actually happened.

There's another DE0-Nano Development Board to be won, but you'll have to listen to find out how to get it.


Best Practices for FPGA Prototyping of MATLAB and Simulink Algorithms

by Stephan van Beek and Sudhir Sharma, MathWorks

As the complexity of modern FPGAs and ASICs increases, engineers are discovering that verification using HDL simulators alone is not enough to fully test system-level design requirements in an efficient and timely manner.

Many engineers are now deploying FPGAs for algorithm acceleration and prototyping. Using FPGAs to process large test data sets enables engineers to rapidly evaluate algorithm and architecture tradeoffs and test designs under real-world scenarios without incurring the heavy time penalty associated with HDL simulators. System-level design and verification tools like MATLAB and Simulink enable engineers to realize these benefits by rapidly prototyping their algorithms on FPGAs.


ARMed and Dangerous

An Outsider’s View of the ARM Cores

by Bryon Moyer

Are you in or are you out?

If you’re out, this is for you. If you’re in, it’s a review.

It’s an ARM core decoder of sorts.

You see, whenever a company like ARM or Intel generates a universe of its own, two things happen. One is that it carries a long legacy, courtesy of its long history. And, as things change, or as the roadmap undergoes strategic alterations, what might have been simple starts to become complex. The burden of acknowledging the past weighs on decisions for the future. If you weren’t an insider, if you weren’t watching all the moves and trying to understand them, you could end up lost and confused.

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