FloTHERM-IC Simplifies Package Characterization
Simple. One number. 180.
The maximum current draw of a bipolar technology PAL16L8A in a 20-pin CERDIP or plastic SKINNY-DIP package across the commercial operating range.
You wanna know how much current must be sourced? Easy. 180 mA. Period.
Ah… those were the days. We were so innocent back then. Somewhere along the way some marketing guy noticed that, especially with the new-fangled CMOS technology, PLD power consumption varied with the pattern in the device. And that was the start of the slippery slope.
Peace and Love and Universal Verification
Dogs need to know who’s on top. They don’t always have to be on top, but they get completely stressed out when they don’t know who is. When a dog with naturally aggressive (or at least assertive) tendencies enters a strange situation, it will act as if it’s in charge. And if nobody objects, then, by gum, it is in charge. If someone objects, well, then a score must be settled, and the newcomer may just have to back down.
And this is often how it works with de facto standards: in order to be the “unified” or “universal” standard, simply declare yourself to be that. If no one objects, then Bingo! You are in fact the universal or unified solution.
Count the number of “universal” solutions you’ve seen. Now count how many are actually considered universal by those competing with the company declaring universality. That percentage is probably reasonably small.
It used to be simple – you designed your chip, converted the gates to a standard interchange format like GDS, taped out by actually writing to big reels of magnetic tape, and threw the reels at the chip maker. A few weeks later the wafers came back. If you were happy to pay a few more tens of thousands of dollars, then you could send copies of the tape to another chip manufacturer to get continuity of supply and to play the competitive pricing game. (OK – the step labelled “design your chip” was, even in the good old days, a slightly more complex step than “first catch your hare.”)
But this is no longer the case.
Moore's law has continued its remorseless march of making device geometry smaller, with the result that chips include many more functions and have become much more complex. At the same time, meeting the requirements of the manufacturing process has become more and more demanding. It is no longer enough to run the layout through a Design for Manufacturing tool before tape out. Instead, even tools at the ESL or architecture planning level need to know details about your target process. Only a little further down the design chain and you are totally dependent on the final process.
I love successful trade shows. I enjoy the buzz of people meeting and doing business, the chance to catch up on the news and the gossip, and the chance to take the temperature of the industry. Used properly, a trade show is part of an engineer’s professional development, not a boondoggle.
One thing that I use as a gauge is who is exhibiting and where they are in the hall, as well as what themes they are pushing. At US shows there is a clear class divide between those with custom-built booths and those in the pipe-and-drape aisles.
Not long ago, IC design engineers gave scarcely a thought to power-related issues. When it came to the cost-benefit analyses of various features on a chip, power was deemed to be more or less free and unlimited. The number of gates, in contrast, was often the expensive crux of the entire design project.
Now the situation is reversed. Thanks to Moore’s Law, gates are all but free while the cost of power – or more specifically, managing things like dynamic power and leakage – is soaring. In fact power could soon be the overarching challenge in IC (and SoC) design for several reasons.
Springsoft Helps Debug Power Issues
It would be a house like no other. Starting with just a bare patch of ground, he could design exactly what he wanted without worrying about what was already in place. This house was, among other things, going to be a green fashion plate. He could design in all the latest tricks and use the coolest technologies.
The key was managing the power. Everything would be in zones, and a central controller, run by a computer, would regulate what went on or off where, as well as providing a fault safeguard in case anything went wrong. The master could always bring down the “grid” to ensure that no one was put in danger, automatically bringing it back up again when things were set back to rights.
Pattern Matching Helps Identify Silicon Suspects
There’s a pretty simple bottom line when designing an IC. Yes, there are functionality requirements, cost goals, performance targets, and any number of must-haves, all of which must be weighed, adjusted, and satisfied. But, given the millions of dollars it costs to buy a set of masks, at the end of it all is one overall abiding mandate: Don’t Screw Up. (That’s the PG version.)
And of course, courtesy of our mushrooming technology complexity, we have at our disposal increasingly diverse ways of screwing up. And none are more daunting than the burgeoning number of restrictions being placed on physical layout.
If there is a hierarchy of techie-ness, analog designers come pretty high-up in the hierarchy. Where digital IC design teams have moved from drawing polygons, through schematic entry to RTL, and are now grappling with ESL tools, the analog guys continue to draw polygons. And analog design is hard: it takes a long time to learn to do, and requires a special mind-set to do it well. This has always been a problem and it is becoming an even more serious problem as analog moves from being a niche activity to something that, if not centre stage, is certainly playing a major supporting role in many devices. Where analog used to be confined to its own chip, SoCs and ASICs are adding areas of analog and mixed signal for greatly increased functionality.
The lack of tools is a problem not only at the layout stage. Compared to the digital world, there are very few tools for simulation, verification and layout and even fewer examples of a complete development tool chain. While some tools do exist, different flavours of SPICE for modelling, for example, they are often difficult to calibrate, complex to use and, despite vendors’ claims, not always as accurate as their digital counterparts. The consequences of a mistake made when implementing a basic element may not emerge until the silicon is under test: by that time the mistake can be difficult to identify and very expensive to fix.
Magma Develops Tekton From a Clean Sheet
How many times have you said, “If I had it all to do over again…”? It’s a natural consequence of the human learning process. Since we’re not privy to the future, we take a direction – some direction typically being preferable to going nowhere at all – and make the best of it. And as we go, we learn what was good and what was bad about that particular direction.
And along the way we’re typically presented with opportunities to make further decisions as forks in the road appear, and, at each such juncture, we can make best use of the knowledge accumulated since the start so that, hopefully, each decision is better than the prior one. And with a little luck, we keep moving forward.
Want to make a small fortune by licensing your engineering designs? Start with a large fortune.
Intellectual property licensing is a popular route for engineering startups. It’s a heck of a lot cheaper than starting a chip company, has low overhead, and promises untold riches. How hard can it be? You hire a few friends, fill the fridge with Red Bull, and spend a few productive hours in front of your computers producing world-beating hardware, software, or middleware. You license your creation for a million dollars a pop, collect downstream royalties on your customers’ products, and spend the rest of your days on the beach getting handed drinks by a man in shorts.
Recent Mergers and Acquisitions
I have a friend who claims that he once worked for four different companies in a year, while not changing desks once. This was in the early days of the EDA industry, during the round of acquisitions that moved the tools for IC design from the hands of proprietary workstation manufacturers to specialist software companies exploiting the relative openness of first Sun workstations and later PCs.
The changes in the embedded tools industry have not been so rapid: someone who worked for i-Logix will have worked for only three companies in two years, during the period when i-Logix was bought by Telelogic, which, in its turn, was bought by IBM.
Why are companies buying other companies? And what does this mean for the developer?
Quantum Dots Go Commercial
We keep remaking the world in ways that nature never could. Or, at least, never did. It started innocently enough centuries ago with humans creating structures that didn’t exist in nature. Then we created materials that don’t occur in nature. We’ve even created elements – lots of them, anything bigger than uranium – that don’t exist in nature. Or at least if they do, we haven’t found them there.
It’s all a process of observing what exists in nature, figuring out how those things work, and then extrapolating from what we have seen to things we haven’t seen. “Well, if that’s true, then this must be possible.” Making predictions based on a theory and then having such predictions proven true or false is one of the cornerstones of how we confirm or refute scientific theories.
And no theory is more mind-boggling than quantum theory. But, as with any theory, if it’s true, then we can coax matter to behave in ways that may have served no purpose in the wild. One such confirmation of quantum theory is manifested in the quaintly-named quantum dot. Yet another artifact conceived wholly within human laboratories.
Until recently, low power designs used a single voltage supply and a host of voltage control techniques such as power domains, power shutdown or power gating, and standby to reduce power consumption. However, process geometries are shrinking rapidly and power is not scaling well, posing a barrier to Moore’s law. Consequently, low power designers have adopted increasingly aggressive techniques such as using multiple supply voltages. Multiple supply voltages imply a design with blocks and cells featuring multiple supply rails, further compounding the already daunting task of verifying low power designs. Incomplete or improper verification of such designs leaves open the possibility of functional failures in silicon.
The Voltage-Frequency Dance
How do you decide on an operating voltage for a design? The question is relevant because voltage and frequency are often opposing requirements in a low power design. Reducing voltage brings about power reduction but has the undesirable effect of limiting the frequency of operation. The answer lies in the maximum targeted frequency of operation. The voltage supplied must be sufficient to allow the transistors to switch fast enough. If you use a single voltage supply for the chip, you end up choosing the lowest operating voltage that facilitates maximum performance, and the power characteristic of the design is limited by the target frequency of operation.
It’s hard to get attention if you’re somewhere people aren’t looking. And, of course, in the world of technology, the focus is usually on the technology. That’s where the innovation tends to be, and, not least important, that’s what’s patentable. At least if it’s hardware, anyway (jury’s still somewhat out on software, although apparently it’s full steam ahead if you’re patenting a living entity… If only Mary Shelley had known…).
Even though technology may be sexy, it doesn’t guarantee success by itself. Innumerable brilliant, interesting technologies have come and gone, leaving few to remember, and fewer yet to pine, their brief existences. And we all know of superior technologies that succumbed to inferior technologies for reasons having nothing to do with technological merit. In fact, we probably use some on a daily basis, although we may not speak the names out loud for fear that the vanquishers may come and break our kneecaps. Or our computers.
Cadence Adds Auto Floorplan Synthesis to Encounter
Design is all about getting from where you are to where you want to be. Only you’re not quite sure how you’re going to get there. In fact, you may not even know exactly where you’re going to end up. It’s almost like being Neil Armstrong or, perhaps better yet, Lewis and Clark. Maybe even the early vanguard crossing the land bridge at what is today’s Bering Strait.
If you think about some of the early explorers, it’s not like they mapped out where they were going, entered it in their GPS, and waited for instructions. “Turn left at the big giant humongous floating collection of plastic trash.” They basically took off somewhere, perhaps thinking they knew where they were going. Like India.