Aloha Time

Tiempo Lets Things Happen When They're Ready to Happen

by Bryon Moyer

Hawaii is a different beast.

It may be part of the US, but things operate with mindset unfamiliar to the typical go-go American, as you’ll immediately discover when waiting to get your rental car.

They refer to it quaintly as “Aloha time.”

For instance, the caterer is supposed to set up at 1 PM. By 2 PM no one as showed up yet. Explanation? “They’re on Aloha time.” Now, this is a problem only if the party is due to start at 2 PM. If, on the other hand, the party is going to start, well, when the party is ready to start, then it doesn’t really matter. Just relax, grab a little refreshment, and let things take care of themselves.

 

Tools, Takeovers, Trivia, and EDA in the Icahn Era

Fish Fry - February 11, 2011

by Amelia Dalton

In Fish Fry this week, Amelia explores the EDA landscape and attempts to discover what the future will hold for the industry. She investigates a new one stop shopping method of marketing in the FPGA world and she also delves into the historical importance of engineering pioneer Ken Olsen. Also this week, Amelia checks out a new truly unique breakthrough in medical technology and awards yet another winner in her series of nerdy giveaways.

 

Out, Damned Spot!

How to Detect Devices Drawing the Life Blood Out of Your Design

by Greg Hackney, Mentor Graphics

Lurking unseen in CMOS designs, unintended devices may be drawing current. As multiple power domains become common, it’s more likely that unintentional forward-biased diodes are introduced in the design. Forward-biased diodes also can be introduced by circuit design errors or layout design errors in complex circuitry such as digital circuits that contain pass gates and analog circuits.

 

Stirring Up Trouble

Altium Designer 10 Kicks Some Serious Sand

by Kevin Morris

Ask someone who sells PCB software for Cadence or Mentor Graphics how often they end up competing with Altium for design seats, and you’re likely to get an answer something like, “Way more often than we’d like.” There is a good reason for this. Altium (formerly ProTel) has been biting the ankles of the big EDA companies, causing trouble for a couple decades on the low-end of board design tools, and, more recently, they’ve been gnawing their way up from the ankles to places where it starts to actually hurt.

Back in the ProTel days, the tools were the working-man’s PCB software. If you weren’t into investing a small fortune in complex workstation-based board design tools, you could snap up a copy of ProTel for a pittance, fire it up on your PC, and do everything you needed to do - without having to hire a CAD department or take out a loan. In recent years, Altium has morphed their tool suite into a complete, integrated solution for electronic product design - including hardware and software.

 

Who Cares?

Is Variation a Real Issue for Designers?

by Bryon Moyer

A couple years ago, the raging topic was DFM, with a heavy focus on litho issues. Curiously enough, part of the conversation consisted of the question, “Is there anything to this DFM stuff, or is it just a bunch of hype?”

The suggestion was that DFM was all about tools guys selling you stuff on the promise that it would help, with you having no real way to prove whether or not it was helping. (No one is going to go through a complete project twice, once with DFM tools and once without them as a control.) So the question was, do users really care about this?

 

Design Tool Death Match: FPGAs, PCBs and We're Caught in the Middle

Fish Fry - February 4, 2011

by Amelia Dalton

In Fish Fry this week, Amelia checks out DesignCon at the Santa Clara Convention Center, interviews Brad Griffin from Cadence about Power Distribution Networks and tries to find out why FPGAs are such bad team players when it comes to board design. Also this week, Amelia answers questions from loyal listeners and offers up another fantastic nerdy giveaway.

 

Using a Hierarchical Approach to Tame SoC Debug Anarchy

by Lauro Rizzatti, EVE-USA

Imagine you’re a private detective and someone hands you a picture. In that picture you see a slim young man in a bathing suit holding a surfboard. The board is plain, marked only with some sort of symbol like a sloppy A within a circle feature. He has dark hair cut into a mohawk, peaked with gel, tinted red at the ends. He’s got a reasonable tan working. Your job is to find this guy. Somewhere in the US. (Let’s assume for the sake of keeping it simple that the guy will be staying put – you won’t be chasing a moving target.)

 

ESL Gambit

Xilinx Acquires AutoESL

by Kevin Morris

In 1995, I strutted my marketing suit onto the stage at the Design Automation Conference and told the world that a revolution was afoot. I had seen the light - the path to engineering enlightenment, the road to the future of design - and I wanted to share. No longer would designers have to toil and struggle with the arcane anachronisms of register-transfer-level descriptions and clock-accurate timing. Now, thanks to the amazing capabilities of high-level synthesis, thousands of lines of detailed and incomprehensible RTL would be replaced by a few elegant lines of ordinary C or C++, with clear and self-explanatory loops and conditionals, that would magically be transformed and re-transformed into whatever hardware

 

Showdown at the “Is My Design OK?” Corral

by Bryon Moyer

There’s a battle shaping up as yet another entrant into the assertion synthesis field makes some noise this week.

We’ve kept an eye on assertion synthesis over the last year or so. Tools and methodology vendors lament that assertion-based verification has been slow to catch on. Some say that’s because it’s too hard to generate and work with assertions. Hence tools to make that easier.

Last summer we reported on NextOp’s entry into the fray. We also noted that their approach was qualitatively different from that of another player, Zocalo, in that Zocalo enables assertion synthesis before the design is done; NextOp generates assertions from RTL already written.

 

Sneaky Bits, Gold Bars and Tiny Packages

Fish Fry - January 28, 2011

by Amelia Dalton

In Fish Fry this week, Amelia delves into sneaky ways to take advantage of the variance found in our semiconductor processes, checks out the variety of features found in the new family of 28nm FPGAs from Altera and discovers a truly unique USB hub from Thanko. Also this week, she looks forward to next week’s DesignCon and announces a winner of last week’s nerdy giveaway.

 

Trading Cards and the Art of Verification

by Matthew Ballance, Mentor Graphics

When I was younger, I briefly became very interested in collecting trading cards – primarily baseball cards. It was always exciting to sort through my weekly pack. However, as time passed and my pile of cards grew, it became more difficult to find the ones that I needed to help fill out my collection. As a kid I was frustrated by what I thought was bad luck. Now years later I understand the math that made that frustration inevitable. It’s the same math that can lead to stymied attempts to achieve functional coverage closure in design verification using random stimulus generation.

 

A PUF Piece

Revealing Secrets Buried Deep Within Your Silicon

by Bryon Moyer

A well-worn literary device in any self-respecting bedtime story ensures us that, no matter how evil the villain, there’s a hidden speck of virtue whereby he or she can achieve redemption.

OK, so I’m not going to go so far as to ascribe literary qualities to these pages, lest credibility be forever lost. But we’re going to take one of the up-and-coming anti-heroes of our time and expose the surprising goodness lurking within.

And who might this beneficent ne’er-do-well be? That infamous processing bugaboo, variation.

Silicon fabrication, like all manufacturing, is about applying order to things. Remaking the world according to our specifications. Entropy is the enemy.

Except when it isn’t.

 

Multi-Core, Self-Test, Robots, World Domination

Fish Fry - January 21, 2011

by Amelia Dalton

In Fish Fry this week, Amelia introduces the fabulousness of the new EE Journal, checks out the new microcontroller-multi-core combo pack from NXP, and tries to sort out the future of chip manufacturing. Also this week, She interviews Kozio co-founder Joe Skazinski, announces a brand new super cool nerdy giveaway and referees a Robot Haiku Smackdown....and here’s a tip, keep listening until the very end...

 

Who is Going to Make Your Chip?

by Dick Selwood

It used to be that real men had fabs. The small number of companies designing chips also developed their own processes and built fabs for only a few tens of millions of dollars. If they had spare capacity they might also run other peoples’ designs through the fab. The fab price tag got bigger as processes chased Moore’s Law, the industry went through cycles of growth and contraction, and lots more people wanted to make chips. So companies were set up just to make chips. These are the foundries.

 

Between an ARM and a Hard Place

Fish Fry - January 14, 2011

by Amelia Dalton

In Fish Fry this week, Amelia examines the new ARM/Microsoft announcement, the squishy ownership of IP in today's electronic design and how the Verizon iPhone plan will affect smartphone users in the U.S.

subscribe to our eda newsletter


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register