Bruggeman Exits Cadence and Forte Makes a Claim for High Level Synthesis
In this week's Fish Fry, Amelia interviews Sean Dart (Forte Design Systems CEO) about where he sees the future of SoC design and how high level synthesis will play a part in the years to come.
Amelia also tries to sort through the details of John Bruggeman's recent departure from Cadence Design Systems as Chief Marketing Officer and investigates how this shift will affect the future of Cadence's EDA360 manifesto.
She has a DE0-Nano Development Board to give out this week, but you'll have to tune in to find out how to win.
Verifying a DSP in an FPGA
FPGAs are an excellent choice for speeding the silicon realization of complex digital signal processing (DSP) algorithms. However, the flexibility of the fabric cannot supplant the complexity of the verification. Traditional FPGA “burn-and-churn” techniques must be replaced with a plan-driven approach that captures the overall verification intent. From there, the randomized tests constructed with Accellera’s Universal Verification Methodology (UVM™) should be combined with formal analysis to predictably converge the verification. With a suitably sophisticated approach, the DSP-FPGA marriage will be a happy one.
POCV is the Latest Salvo in Improving Timing Analysis Accuracy
When I was a teen, I remember someone coming to help my Dad plan a big move of some piece of equipment on our orchard. What struck me was how this guy could pre-visualize all the various scenarios and then consider the consequences and, in particular, all the things that could possibly go wrong for the different cases.
I was pretty impressed. It seemed like such thorough analytical capabilities were a skill and a gift. Over time, however, I’ve noticed that such an ability isn’t always appreciated. Because most of the world likes to assume best-case conditions, the “value add” of the more thorough approach is to point out that there are potential negative consequences too. Which makes you Mr. Negative. The pessimist. Always there to dash cold water on a hot idea. Doesn’t matter if you’re right.
3D gets lots of attention these days. Whether it’s the massive success of a movie that spawns a gaggle of followers making every possible consumer item 3D, the added dimension of the fin on a FinFET (or tri-gate) transistor, or the stacking of chips using TSVs or other technology, you just can’t seem to go wrong with 3D.
Finding that Happy Medium
I used to be a die-hard manual transmission driver. Even before I drove a car, I had learned how to double-clutch for smooth on-the-go gear changing on our Case tractor (which didn’t have synchronized gears because it wasn’t intended to be shifted on the go). My grandmother insisted on a manual transmission up until she stopped driving in her 80s (or later?): “I vant to do it myself!” (That’s a Swiss-German accent there…)
I finally had to rethink my principles when I got a cell phone. The moment of truth came when I was at a stoplight waiting to turn left while talking on the phone. The light turned green and I proceeded, but realized I didn’t have enough hands: I needed to turn, change gears, and hold the phone, all at the same time.
Lauro Rizzatti Talks Emulation and IBM's New Memory
In this week's Fish Fry, Amelia interviews Lauro Rizzatti (Vice President of Marketing, GM of EVE-USA) about emulation, verification, and why Lauro thought he was planting pepperoni in his garden in Italy.
Also this week, Amelia checks out the new phase change memory unveiled by IBM and investigates how this new memory technology may change the electronics industry as we know it.
Amelia has a fun new nerdy giveaway to give out this week, but you'll have to listen to find out exactly what it is!
Does a Standards-Based IP Strategy Hurt Competition?
In today’s global electronics economy and, more important, global techonomy, successful companies have to make careful decisions where they will differentiate and where they will standardize. Nowhere is this more evident and crucial than in the fabless semiconductor arena. Since fabless companies have (as the name implies) no fab, they logically do not have the ability to differentiate themselves from their competition by superior semiconductor technology.
Of course, you wouldn’t know that if you listen to FPGA companies.
OneSpin Takes on Formal Verification Metrics
“Is this it?”
“Yeah, I think so. Drop it off here.”
“Whaddaya mean, ‘I think so’? If they don’t get the money, we’re dead.”
“I know, I know. But you can’t see any addresses here. It’s all so beat up I don’t really know which house is which.”
“And you had to go without a map. Real smart.”
“There is no map, you moron! Not even Google will drive through this neighborhood. This is, like, No Man’s Land. I just want to get in, make the drop, and get out. Look, there, those guys are watching us. Givin’ me the creeps.”
The Intersection Between Sailing and Engineering and the World's First Foot USB Controller
In this week's Fish Fry, Amelia chats with Bill Neifert (Carbon Design Systems' Chief Technology Officer) about the benefits of Carbon's pre-silicon software development and architectural analysis, and how his love of sailing intersects with his passion for engineering.
Also this week, Amelia gets into the nitty gritty details of a new 3D printer specifically created to print chocolate, and she investigates how the new foot-operated digital interface unveiled by KMI might not be all that they claim it is.
Amelia has a Lattice ECP3 Versa Development Kit to give out this week, but you'll have to tune in to find out how to win.
Many of today’s integrated-circuits (ICs) are designed to operate in low-power modes to accommodate greater analog-digital integration, faster operating frequencies, and battery-powered applications. During semiconductor manufacturing test, the majority of logic is often activated concurrently to facilitate detection of many faults within a small set of patterns to reduce test time. Activating all the logic at once uses more power than these low-power devices were designed to function under, which can cause them to fail or burn out during test.
This divergence in functional power versus test power means that the test application has to allow power thresholds to be set so that overstressing devices beyond the functional design and operation is avoided.
Happy Birthday, the United States of America. How does it feel to be 235? You really have done well since you took the training wheels off and started riding your bicycle by yourself.
Many societies have what historians call “Foundation Myths” – stories that explain how a community was established. Some myths explain societies through the acts of gods, others through the actions of people, either imaginary or real people. For example, the founding myth of the City of Rome was that twins, Romulus and Remus, who were brought up by a she-wolf, founded the city that was the heart of the Roman Empire.
Bruggeman Takes On EDA
At the Design Automation Conference this year, Amelia had the pleasure of sitting down with Cadence CMO John Bruggeman and they chatted about all sorts of things...including why he thinks the "style" of EDA needs re-invention, where he thinks EDA360 is headed, and why he believes EDA isn't getting its fair share of the electronic market revenue pie.
Also this week, Amelia has a Lattice ECP3 Versa Development Kit to give out to one lucky listener, but you'll have to tune in to find out how to win.
Synopsys’ OSG Group Helps Designers Put Photons in the Right Place
Way back in the 80s, I remember talking to someone about the delicacy of putting together the lens stack used to project the light that exposes circuit patterns onto silicon wafers. Those machines must seem hopelessly primitive today (pellicles were just being introduced), and yet, even then, the optics were a delicate matter.
As described to me, the lenses were carefully ground and assembled with thin sheets of paper between them – like the wax paper that keeps slices of deli cheese from sticking together. To assemble, you carefully positioned one lens over its adjoining one, and, when alignment was perfect, you gently slid the paper out. If you got it wrong, there was no return once the paper was removed: the lenses were so precisely ground that the cohesive attraction between the two lenses would make any further minute adjustments impossible.
Who’ll Use the Next Generation of Design Tools?
The Von Neumann architecture is a miracle of efficiency if you count the algorithmic complexity that can be completed by any given number of transistors. If you’ve got enough transistors to create a 32-bit processor plus peripherals plus enough memory to store a decent size program, you can execute an enormously complicated algorithm.
Where Von Neumann isn’t so efficient is in the amount of computation for a given amount of power, or in the number of computations in a given amount of time. Those battles are won handily by custom, parallel hardware like we might create in an FPGA, or in a custom, algorithm-specific block in an ASIC or custom SoC. Optimized hardware that specifically implements our algorithm will always win in terms of speed and power - at a cost of vastly increased transistor count.
Imagination Technologies Tries to Make it Easier to Connect from Anything
Being out in the wild is supposed to get you away from things modern and technological. And yet… there are ways that new gadgetry might improve your isolated camping experience.
Let’s say, for example, that a critical camping information system would be useful. Perhaps it would link to a variety of on-line video channels dedicated to camping content. And, rather than packing yet another device, perhaps it could be integrated into an existing piece of camping equipment. Like, perhaps, your camp stove. It’s got a lid that flips up to block the wind – why not integrate a screen into it?