MATLAB to Hardware

MathWorks Automates HDL Creation

by Kevin Morris

Quick! What’s the fourth largest EDA company in the world? Most of us in the industry can rattle off the “Big 3” right? “Daisy, Mentor, Valid.” Oops, my time machine was off by about 30 years. How about “Synopsys, Mentor, Cadence”? After that, it gets a bit dicey - if we counted Magma, that would be a possibility, but we need to chalk them up to Synopsys now. For those of us who think FPGA companies are actually EDA companies with a different business model, Xilinx and Altera would be in the top four or five. Beyond that, it drops off -- a lot.


V for Verification

DVCon 2012 Breakdown

by Amelia Dalton

Welcome to the soothing waters of verification. Jump right in, the water is warm! This week's Fish Fry is all about design verification and DVCon 2012. I sift through all of the details of this year's show: the keynote, the various announcements unveiled at the show, the happy hour expo show hours and even the eerie decor of the Doubletree Hotel. In a special DVCon interview double header I chat with both Shakeel Jeeawoody (Blue Pearl Software) about getting your constraints right for HDL-based designs, and I also chat with Anupam Bakshi (CEO - Agnisys) about how Agnisys is attacking a brand new part of the EDA/verification market.


One Ecosystem to Rule Them All

Altium's Innovations, Death Star BOM and Retro Games

by Amelia Dalton

In this week's Fish Fry, I look at the importance of ecosystems - in today's electronic products as well as in the tools we use as designers. I chat with Sam Sattel of Altium - one of the most progressive companies in the industry in establishing a cloud-based ecosystem for electronic design. We discuss the most recent innovations at Altium, including the new tools available in Altium Designer and the interesting way Altium deals with software updates. This week I also look into the projected BOM cost for a real-life Death Star and unveil my favorite place to play retro video games.


Tabula Taps Intel

22nm Tri-Gate Process Should Bring Rewards

by Kevin Morris

We all knew it was coming, but Tabula “officially” announced this week that they are producing their next yet-to-be-announced family of FPGAs on Intel’s 22nm Tri-Gate process. As one of the worst-kept secrets in the programmable logic industry, the Intel-Tabula relationship hardly comes as a surprise. The announcement was widely leaked about a year ago when Achronix formally announced a similar relationship with Intel.

What does it all mean?


Real-World Issues at 28 nm

Cadence and Samsung Do Some Pipe Cleaning

by Bryon Moyer

Semiconductor technology just gets curiouser and curiouser as feature sizes shrink. In real life, that means that EDA tools have to work harder and harder to figure out what’s going on and help engineers implement enormously complex designs. As usual, the problem can be boiled down to things that didn't use to matter becoming a problem

Of course, at the extremely tiny level anticipated by technologies like carbon nanotubes, things change completely. But that's still research. Leading-edge designs today are still using "conventional" processing, but making a real design work isn't easy.


All You Need Is Love

(and Some Good Tools)

by Amelia Dalton

PCB problems got you all tangled up and blue? Never fear, all you need is love. Well, that and some good tools. This week my guest is Steve McKinney (Mentor Graphics). Steve and I are going to talk to about Mentor’s HyperLynx tool suite and why the newest features of this tool may make those pesky PCB problems a thing of the past. Also this week, check out why power and system management decisions might best be made sooner than later.


They Want Your Brains

EDA is Not Quite Dead After All

by Kevin Morris

When companies become zombies, it’s not quite as obvious as with humans. Sure, the symptoms are similar - being dead but walking around as if still alive, no capacity for rational thought, pursuit of a single-minded hunger - all while the inside is rapidly decomposing. Oh, and then there’s the smell.

The Moore’s Law apocalypse is taking place in the world of custom chip design right now, and by all rights EDA companies should be among the walking dead - mindlessly scouring the engineering countryside for leftover morsels of brains.


Tools for the Gifted

Packet Plus Brings Debugging to Networking Engineers

by Kevin Morris

Networking engineers are some of the best and brightest among us. There are good reasons for this. Designing networking equipment is a demanding discipline, spanning a wide gamut of areas from analog and signal integrity to digital design to software - and integrating all of these elements at something near their maximum performance potential. In order to get a competitive piece of network hardware out the door, you are literally designing at the bleeding edge of everything.


Why Use an 8-bit Core When 32 Bits Are Better?

by Dick Selwood

You are designing a new product as an SoC and need some processing power - not a huge amount - and you have tight power and real estate budgets. So you drop in an 8051 core. Job done? Well, not according to the folks at Cortus. These guys, a multinational mix of people based in the Southern French town of Montpellier, whose backgrounds include working on processors for Intel, Bosch, Infineon, Siemens, and Synopsys, are likely to say that you may have made a poor move. Your real estate and power budgets can be achieved with a processor that will also give you a great deal more processing horsepower and a lower overall cost of ownership - their APS3 32-bit core.


Looking Back on Five Years

by Dick Selwood

During the Christmas break, I took time out from roasting an ox on the open fire, distributing presents to the assembled multitude of staff, chasing foxes across the rolling acres of Selwood Towers and feasting, wassailing and carousing to think about the past year and embedded technology stuff. I managed to overcome the urge and went back to roasting an ox etc, but, now the break is over, it seems worth having another think.


The Valley of FPGA

Where Green Pastures End

by Kevin Morris

Just about every electronic technology on the market today has alternatives. Between custom chips, ASSPs, pre-built modules, embedded processors, microcontrollers, FPGAs, and a host of other silicon-based goodies, there are always numerous ways to solve any given problem. As engineers, we make our choice based on any number of criteria - cost, power, size, reliability, our familiarity and experience with the technology, our company’s preferences... all of them weigh into our decision.


A Memristor By Any Other Name?

by Bryon Moyer

Perhaps you’re new to the US and you’re investigating some recipes to make. You’ve resigned yourself to the fact that, here, things are measured more by volume than by weight, and the measurement units have that peculiar non-metric feel about them that forces you to prove you can still do mental arithmetic. But the terms for things are sometimes different too, even if you come from another purported English-speaking country. We don’t do aubergines and courgettes; we do eggplants and zucchini.


It Has to Get Better

A Look Back at 2011

by Kevin Morris

Yawn! Another boring year of exponential improvement in capability, cost, and power consumption. Bo-o-oring. When will something truly exciting happen in electronics? It’s just the same old grind, year after year, with nothing all that interesting going on.

Moore’s Law is a harsh mistress. It sets the bar for our industry at an incredibly high level. If you manage a 2x improvement in everything you do every two years, there’s not really anything of interest to report. You met the standard - status quo - move on along - nothing to see here. Furthermore, if you try to brag that you’ve “doubled” this or “ten-times’d” that, you get thrown into the bin of “marketing-hypers” and your credibility plummets.


Bashing Bugs

by Dick Selwood

Horrendous quote of the day – “27% of the industry requires 3 or more spins.” This is the headline on a slide from Harry Foster, of Mentor, based on a large worldwide survey of silicon and FPGA implementers and their verification problems, conducted by Wilson Research in 2010. OK, the positive side is that 73% get it right by second spin, and a further 23% by the fourth time round. But with spins costing multiple millions of dollars, you have to have a huge market for a chip to justify that number of spins, and a market that is prepared to wait for the chip to arrive, since, by most estimates, a re-spin is going to take three or more months. And re-spins are only part of the reason why 66% of projects are delivered late.


Adventures in EDA Land

How EDA and Disneyland May Have More In Common Than You Think

by Amelia Dalton

Did you ever consider that EDA is a lot like Disneyland? I know it may sound a little kooky but check out this week’s Fish Fry to find out more! I interview Shawn McCloud (Vice President of Marketing - Calypto Design Services) about Catapult-C’s transition to Calypto, the ambiguous nature of the term ESL, and what Calypto brings to the EDA party. Also this week, I interview Shishpal Rawat (Accellera Chair) about why it's important to have IP standards and where he sees IP and system design standards headed.

subscribe to our eda newsletter

Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register