ASIC Analytic Looks for Anomalies in the EDIF File
“Somethin’ just ain’t right about that boy.”
She snuck a sideways glance at him sitting alone at the counter, nursing a cup of coffee, rumpled like he just woke up in those clothes, oblivious to the furtive comments of those sizing him up at the nearby table. “Yep, I cain’t quite put my finger on it,” she continued, “but he ain’t from this county, that’s for sure. He don’t look folk in the eye, he pert near run me down on the sidewalk th’other day not watchin’ where he was a’goin’. He don’t seem to have a job or nuthin. Just ain’t right in the head, I’m thinkin’.”
“Oh, come on Mae, you’re always getting’ all suspicious and such about new folk. What’s he done to hurt you?”
MethodICs Introduces ProjectIC for Enterprise Project Data Management
So you’re doing a design of this clever, dashy little inner-city small-but-fast car. And, like everyone else, you’re not doing it all 100% by yourself. You’ve invented the wheel enough times to where the thrill is pretty much gone; you’re going to buy some wheels instead and focus your efforts, maybe, on infotainment instead. You know, nothing takes the boredom out of downtown traffic like a video and the ability to update your Facebook page with one hand while you drive with the other and talk on your phone with the other.
And there’s plenty of other stuff you don’t want to redo yet again. So you unearth some of your old moldy dashboard designs. And you pull in some reclining seat IP. And you buy some rear-view-mirror verification models. And there’s this project that someone else at your company did last year where they came up with a high-performance wheel that was really awesome, so you re-use that (after the guy managed to dig up the old design files).
Vennsa Tries to Figure Out Who Screwed Up
Several years ago, while renting a vehicle for an event I was going to attend, the rental guy pointed out that my driver’s license had expired a couple months prior. So he couldn’t rent me the vehicle. My wife at the time bailed me out, but I decided to postpone my departure by a day to avoid the risk of getting pulled over with no license to show. Which meant an emergency trip to the DMV.
I found that I could get licensed quickly, but I had to take the written test in order to do so – something I hadn’t taken (or studied for) since I was a teenager. So, with no preparation, I went off and answered the questions, knowing that these tests have a history of being flaky, and nervous that my ability to drive legally lay in the balance.
I don’t remember what the numbers are, but you aren’t allowed to miss many. And I missed one too many. And I asked about the questions, and there was one in particular that stood out:
Docea Makes the Peace
In the defender’s corner, wearing the blue trunks, with several years of evolution under its belt, scoring knockouts against low-level transistor power simulation and having captured RTL level simulation, with an eye on raising the level of abstraction to TLM and above, reading in UPF and CPF formats, displaying a wide range of views and analyses, the new rising star in a league that’s been dominated by performance, the current champion, going with the flow, fighting the powers that be, Powerrrrrrrrrrrr Simulatioooooooooon!
And in the challenger’s corner, wearing the red trunks, just arrived from the mechanical world, displaying its might with full finite element analysis as well as lightweight prowess for standardized packages, putting packaging to the test, taking center stage in 3D chips, highlighting who’s hot and who’s not, showing the glow as it goes, providing the “hot” in the hot spot, beating the heat in the hot seat, Thermaaaaaaaal Simulatioooooon!
Exactly ten years ago I was helping Adaptive Silicon, a start-up, with their European marketing. The company had a great pedigree, with roots in National Semiconductor and financial and process support from LSI Logic and financial and tools support from Synplicity. (For new readers - LSI Logic is now LSI Corporation and is no longer an ASIC company, as it was then. Synplicity was an independent company supplying EDA tools for FPGAs and is now part of Synopsys.)
The product was an FPGA technology for integration into ASICs and SoCs. The idea was that, within the design, small blocks of FPGA fabric would provide significant flexibility. For example, by adding programmability, it should be possible to fine-tune the design without a re-spin. The same properties would allow a basic design to be programmed to make different members of the same family by changing features in the FPGA area. One use that was particularly attractive was for a product being developed to meet a standard that was not yet finalised: the logic for the standard could be implemented in the FPGA and then field-upgraded when the standard was ratified.
It better be fast.
Whatever it is, whatever it does, it’s all good as long as it’s fast.
We live for speed in our supercharged world. After all, we’ve gone from a society that used to survive on one breadwinner per family to a society with two breadwinners as the norm to the point where some people have to have multiple jobs just so they don’t fall behind. (Well, in the US, anyway.) So we’re busy. Very busy. And we have to toss Facebook updates and tweets in on top of that.
So we have to be able to do things fast.
And your boss promised something impossible to his boss who promised something even less possible to his boss and so on up to the CEO who promised something ridiculous to the Board so that the share price could hopefully go way up for at least a few days and make them a boatload of money. So it’s your responsibility to figure out how to make the impossible, nay, the ridiculous, happen. Now. You’re going to be a busy dude and it’s your fault if it doesn’t happen on time.
Cutting corners never seemed like cutting corners before. It seemed like a practical way to handle real-world problems. You don’t want to make any problem more complex than it needs to be or it will be hard to solve on an everyday basis. So you simplify.
But if the world gets more complicated, then what were once practical simplifications now look like cutting corners, and it’s no longer acceptable.
And so it goes with RC extraction tools. You just can’t ignore the things you used to be able to ignore. This sleepy little corner of EDA has historically drifted quietly along in the shadows, but, more recently, has made some moves towards the spotlight.
And for good reason. The crazy geometries being built in foundries result in all kinds of interactions that never used to occur (or matter). So the simple rule-based approaches of yesteryear are quickly giving way to sophisticated mathematical juggernauts; the question is, how do you balance accuracy against the amount of time it takes to calculate?
From Vertical to Horizontal to Vertical
Axiom 1: No matter what we’re doing, something else seems like a better idea. In many cases this takes us forward in a circuitous semi-linear manner towards something new. We may get there by precise navigation, or, more typically, we arrive in a Brownian random-walk kind of mode – after which we can claim credit for great prescience.
Axiom 2: We have short memories. We look forward, not backward. No wasting time on “been there, done that” when we can focus on “wanna go there, wanna do that.” (Or more succinctly expressed in the modern vernacular simply as “Want!”)
Axiom 3: One leg is shorter than the other. This means that, without suitable points of reference, we tend to walk in circles.
Different Approaches to Feeding SVA Engines
Point: Assertions are a useful way of verifying the full spectrum of behavior of a piece of circuitry.
Point: The use of assertions has not taken off as quickly as one might expect, given how useful they can be.
Point: A main limiting factor for the use of assertions is their complexity for anything but simple cases; they can be hard to read and harder to write.
This is about as far as we can go with reasonable consensus. Here we come face to face with various ways of solving that last point, and that’s where we go off in a couple different directions. There are a number of formal tools out there just aching for more assertions to prove, so anything that can help to create assertions will make them happy.
Sapient IC Aims to Boost Control and Confidence
Product life-cycle management tools are a double-edged sword. They help to solve a serious problem by standardizing how things are done and reducing uncertainty, but they can end up bogging a company down in process and tools development. The more complex the product whose life is being managed, the more this is true.
The name ‘life-cycle” would indicate a womb-to-tomb scope, and it often is, but the challenges of such tools also accrue to the somewhat less comprehensive tools that cover just one major element of the life cycle, whether that be development, production management, or end-of-life management. Even those phases of a product’s life, taken alone, can be inordinately complex.
Is HLS Ready for AARP?
It’s a done deal.
OK, maybe not done, but getting done. It’s the long tail, the asymptote, the 20% that takes 80% of the effort.
Put simply, it’s mature. Or -ing.
Having just announced a new Blue Book (more on that in a minute) and incorporation into TSMC’s Reference Flow 11, Mentor is heralding the coming of age of electronic system-level (ESL) design aka High-Level Synthesis (HLS) aka C-to-RTL, most notably in the embodiment of their Catapult C tool. Taken at face value, and given the sketchy history of this technology, this is actually a big deal. However, there are others that may have reason to say, “Not so fast!” It remains to be seen whether there is consensus on this fact.
First, what does it mean for “tools” or “methodologies” to become mature? This generally means that the major technology developments necessary to make a technology useful are in place; further work involves refinements. A debatable corollary to that would be that it’s no longer an interesting technology to work on since the cool stuff has been done.
A Panel Discussion
I’m a failure.
Utter and complete.
You see, we journalists are supposed to stir things up, get someone’s dander up, rouse some rabble. And panels can be the best way to do this. Get a group of spirited experts together, whisper to them what the others said about their mothers, and let nature take its course.
It’s all good fun. For us. And everyone else gets over it. Eventually. And it’s not even hard.
So a recent discussion I was privileged to conduct can, by these standards, only be considered an epic fail. Granted, this wasn’t a public panel, so any dramatics would have been of value only to me; thus the consequences of my failure are less dire. But only by degrees.
The Atrenta team recently convened a collection of minds to discuss IP quality. And, while everyone brought a different perspective, there was general agreement around the table on the points made.
It Takes Three – er – Four to Tangle
Last year I tried to wade through the world of emulation to untangle it a bit. It all seemed so simple at the time. Once I had it untangled, that is. Problem is, I only thought I had untangled it. Cadence recently announced a “unification” (there’s that word again) between simulation, simulation acceleration, and emulation. And it became pretty clear pretty quickly that, in the intervening year, a new tangled web has replaced the one I thought I had cleared out before.
Bottom line, I got confused. Again.
OK, perhaps that’s not such a rare occurrence, but work with me here…
As I started talking around, it felt like I wasn’t the only one confused. Although, in truth, you never think you’re confused until you realize that other people adhere to other beliefs with the same level of conviction that you adhere to yours. So everyone has more or less a clear opinion, it’s just that they don’t all align. And so I get confused. And so, in turn, I try my best to share my confusion with the others in an attempt to illustrate that there’s confusion.
Fixing the ‘Anti-Social’ World of EDA Tools
In an ideal world, EDA tools would represent a perfect match for the chip engineer’s needs, and their use model would be architected to match his design flow rather than the other way around. In the real, Perl-script infested world, EDA tools are islands between which users must build their own bridges. Moves toward data consistency help to some extent, but beyond that things become very cumbersome. Decisions made to address one problem, let’s say power consumption, can have an adverse affect on another, such as timing. In a world of point tools there is a distinct lack of multi-disciplinary intelligence. As a consequence, design closure when faced with the contradictory constraints of today’s multi-scenario designs, is in many cases unobtainable.
One area where this problem has been conquered is logic synthesis. When faced with multiple conflicting constraints (timing vs. area for example) synthesis tools have the visibility to make trade-offs – keeping one in mind when optimizing another. It would be unthinkable to run one tool to optimize timing and another to optimize area. But that’s what we have in areas like power and clock synchronizer setup, where optimizations made to meet power consumption targets can undo the careful efforts to make the design ‘clock domain crossing (CDC) clean’.
FloTHERM-IC Simplifies Package Characterization
Simple. One number. 180.
The maximum current draw of a bipolar technology PAL16L8A in a 20-pin CERDIP or plastic SKINNY-DIP package across the commercial operating range.
You wanna know how much current must be sourced? Easy. 180 mA. Period.
Ah… those were the days. We were so innocent back then. Somewhere along the way some marketing guy noticed that, especially with the new-fangled CMOS technology, PLD power consumption varied with the pattern in the device. And that was the start of the slippery slope.