From Conductor to Semi

by Bryon Moyer

“So why do you think you’re right for this job?

“Well, it’s pretty much exactly what I’ve done for the last 10 years. We were almost done with something just like what you’re about to develop when the economy tanked and the project got canceled.”

“Hmmm… OK, which defrumpitation algorithm did you use?”

“Well, we started with the FTL-25 open-source algorithm…”

“OK, good, that’s what we’re using…”

“… yeah, but we found that performance was horrible – it’s really inefficiently put together. We pretty much had to develop a new one from scratch. It took a lot of tries to get it just right – it’s not obvious – but we managed it. We were going to publish the results, but it all got packed up before we had a chance to.”

 

Timing Closure in 2011

What Is the Key?

by Ron Craig, Atrenta Inc. and Bob Smith, Magma Design Automation

[Editor’s note: Atrenta’s Ron Craig and Magma’s Bob Smith got together to provide two viewpoints on what is going to be most important for timing closure in 2011. What follow are their thoughts.]

What is timing closure in the 2011 SoC design environment? Ron Craig, Senior Marketing Manager, Atrenta Inc.

Backend timing closure is an incredibly inefficient process, fraught with uncertainty. In an ideal world, an engineer would need to run a single pass through the synthesis to GDSII flow and he'd be done. But the reality isn't that simple. I've heard stories from well-known companies of up to 20 backend iterations to close timing, with each iteration taking up to a week. Evidence such as this would suggest that timing closure in the backend is no longer working – that this “tortoise” will indeed eventually get there, but at what cost? Is there a way to add certainty to the process?

 

Mentor Graphics

Graphics Mentor

by Jim Turley

Engineers of a certain age will remember when Mentor Graphics made engineering workstations. Remember those? They were overpriced computers with big monitors that every self-respecting hardware or software designer had on his/her desk, as opposed to a Windows or Macintosh machine that marked you as a receptionist, or worse, a marketing dweeb.

Mentor was just one of many companies making engineering workstations, including Apollo, Daisy, Intergraph, and Sun Microsystems. Remember them? Unlike most of its competitors, however, Mentor Graphics survived. Flourished, even. Mentor is now a big embedded-development company with all kinds of spiffy technology to help hardware and software designers.

 

Head in the Clouds

Altium Leads Another Design Tool Revolution

by Kevin Morris

Nick Martin, the founder of EDA’s most unconventional company, Altium, Ltd., is not afraid of being different. Since 1985 when the company (formerly known as Protel) released its first EDA tool, Nick and his growing band of nerdy rebels have been challenging the status quo in electronic design automation. The company has always had the philosophy of giving the individual engineer the tools he or she needs to get their job done, without the barriers of cost and access posed by traditional EDA.

Nick’s vision has always extended beyond the here and now. The self-appointed vanguard of the constantly moving target of innovation has capitalized on the company’s unique circumstances and culture to produce products and services that track dangerously close to that bleeding-edge of engineering design - where the concepts embodied by the design tool flow are just a little ahead of the mainstream engineering crowd, but well within view of forward-thinking designers.

 

To Err Is Universal

by Bryon Moyer

Listening to Alexander Pope (and even Seneca and Cicero long before), you would think that erring is a particularly human trait. Taken out of the original context (which places human fallibility in contrast to the divinity of forgiveness or the diabolicalness of persisting in erring), you might feel singled out by nature as a particularly unreliable entity.

In fact, we are surrounded by errors. They happen all the time. We are but a wee part of a huge, interconnected, error-prone system. Our very existence is a testament to the ability of living forms to survive any number of errors that might occur. The more we study genetics and the geological history of our planet, the more we learn about the range of redundant systems and adaptations that have evolved to bring us this far. (Or, looked at from an anthropic perspective, that had to evolve to get us this far.)

With a few exceptions, however, the machines we humans create have no such adaptability. Whereas the natural world abides variation and randomness, we create deterministic systems that assume a relatively narrow range of operating conditions such that a given input will guarantee a correct output.

 

Chips - Not Just For Kids

Fish Fry - December 10, 2010

by Amelia Dalton

In Fish Fry this week, Amelia examines where our chips come from, the new Xilinx (TI enhanced) DSP kit, statistical variations in semiconductor processes, and some seriously bad movie tech. Also this week, the nerdy giveaway is a Texas Instruments Wireless Watch Development Tool.

 

Statistical Variation

by Dick Selwood

Your burger bun has seeds on it, and they look as though they are randomly placed, (I am sure that in the bun factory there is a standard procedure that says how many seeds should go on each bun, and this is accurate when averaged out across the buns.). If you put a large coin on the surface of your bun, how many seeds does it cover? Try somewhere else, and then somewhere else again. Each time you will get a slightly different number. Now try a small coin. The numbers will, it is likely, vary even more.

Now, instead of two dimensions, think three. And instead of a burger bun, think of the silicon in a 22nm technology, with sesame seeds as your dopant atoms. At this level we are looking at a very small number of atoms of dopant, and while the manufacturing procedure will have an average doping level across the entire device, two otherwise identical transistors will have different numbers of dopant atoms. In fact, one transistor in 22nm technology may have ten or even fewer dopant atoms, while another may have twenty, or even more. This is going to produce correspondingly different characteristics.

 

Visualization for Chip Design

by Aditya Ramachandran, Synopsys

You’ve heard it a hundred times: “Lower the costs, complete the project on time and don’t make any mistakes.” This is the mantra of just about every product development organization in the world. Within the semiconductor industry this translates into lowering product lifecycle costs, getting designs taped out on time and avoiding bugs that require respins, according to a recent International Business Strategies (IBS) survey [1]. Achieving these formidable objectives requires design teams to continue to improve design productivity and eliminate errors in their work product. An important component of improving productivity and reducing errors is having easy and real-time access to key project data that design teams can leverage into smarter decision making. At the same time, there’s increasing recognition that not only the technical leaders need consistent project visibility, but business and management leaders do as well. An unpredictable, poorly timed product release can have the same dire consequences as a very late one. Tools and/or processes that can automate and present a common, unbiased view of key project metrics to the entire team of project stakeholders are especially valuable. That’s where visualization can help.

 

Calling All Plant Cars

Fish Fry - December 3, 2010

by Amelia Dalton

In Fish Fry this week, Amelia investigates the curious case of QuickLogic, Lattice Semiconductor’s new HiGig MAC IP Core, and Mercedes Benz’ new Biome concept car. Also this week, she announces the winner of the very first Fish Fry nerdy giveaway.

 

You Got Your Peanut Butter on My Fabric

Why FPGAs Will Win

by Kevin Morris

You probably remember the TV commercials. Two strangers randomly collide - co-mingling their confections in a fictitious fortuitous coincidence - giving the world the magic that is Reese’s Peanut Butter Cups. It’s a lie, but fact emerges from farce - chocolate and peanut butter make a very nice combination.

FPGA fabric and optimized circuit blocks make a very nice combination, too. Why settle for lower performance, lower density, and higher power consumption for the parts of your circuit that do not require the flexibility of FPGA fabric? Why pour concrete and lock down chunks of your design in hard-core cells that are likely to change or require multiple variants?

 

A Few Rounds on EDA360

by Bryon Moyer

Several months ago, Cadence announced a strategy called EDA360. It was accompanied by a whitepaper that was eventually made public. It was, and is, billed as the brainchild of Cadence CMO John Bruggeman and was issued as a call to arms – a manifesto, even – to the EDA industry.

And it caused a bit of a stir, some of it the kind Cadence would like, some less so.

Well, now that some time has passed to let everyone calm down some, seems like it might be good to come back to this topic in the hope that rational heads can prevail. What does this mean for Cadence and for the industry?

OK, that sounds way too generic. Here’s the real question people ask: is this just marketing hype or is there some substance behind it? The specific reason that question applies is that most examples given by Cadence about how EDA360 gets put into play involve pointing to products that have existed long before EDA360. Which almost makes it look like the strategy is really a repositioning of existing products.

 

ARM, EDA and MachXO, Oh My!

Fish Fry - November 12, 2010

by Amelia Dalton

In this week's Fish Fry, Amelia takes on ARM Devcon, the Ultimate EDA tool, Lattice Semiconductor's new MachXO2, 50 caliber flash drives, and more...

 

ARM’s Cortex-A15 “Eagle” Has Landed

by Jim Turley

You know who you are. You’re one of the legions of ARM programmers, engineers, and developers. You made ARM the most popular 32-bit processor on the planet—eclipsing even Intel. You use an ARM-based cell phone, you listen to your ARM-based iPod, you spin up ARM-based disk drives… admit it. You’re part of the ARM army.

Well, good news, campers. The latest, greatest, fastest, most wonderful-est ARM processor in the world just got announced today. It’s the tippy-top of ARM’s broad family tree, surpassing even the multicore Cortex-A9. Behold the Cortex-A15. Look upon it and be amazed.

Okay, maybe the A15 isn’t that big a deal. Yes, it’s a sophisticated and advanced 32-bit processor design, and it’s clearly the best work that ARM has ever done. But to be honest… it’s a lot like other 32-bit designs from other CPU companies. The big deal is that it’s the most-advanced CPU from ARM. It’s just not the most-advanced CPU ever.

 

Maximizing Utility

by Bryon Moyer

Conventional economic theory has had a pretty tough couple of years. Markets didn’t behave like markets should have behaved. “Irrationality,” in an exuberant guise, toppled, or threatened to topple, some august institutions.

Of course, any time behavior starts to threaten orthodoxy, it’s explained away in some fashion that fits the orthodoxy for as long as possible. During the Great Depression, when contemporary economic theory didn’t allow for the existence of a depression, upon seeing some bedraggled gentlemen selling old fruit by the side of the road as an only means of eking out a bit of coin, Hoover is said to have commented on the vibrancy of the economy that these entrepreneurial fellows proved.

Today the topic is markets. The meaning of free markets, fair markets, whether to ratchet down, regulate, rampage (with some voices shrieking with every possible limit on behavior, “You’re threatening innovation!!!”), and, of course, what the right thing to do is.

 

Moving Back In Time

Or How to Make Your Giant SoC Look Like a 286

by Bryon Moyer

You take a bit of extra logic, tap into your JTAG infrastructure (pun intended), add some IP, and look into what’s happening with your FPGA. And you’d say, “Oh, that sounds like Altera’s SignalTap or Xilinx’s ChipScope.”

OK, so then say you add some logic to your ASIC, capture and compress a bunch of data, and decompress it on the way out. And you’d say, hey, that sounds sort of like DFT (Design for Test) technology. Sort of. Maybe. (With DFT, usually the stimulus, not the result, comes in compressed and is decompressed on-chip, but it has a similar feel.) Or you say, hey, that sounds like the debug infrastructure that ARM and MIPS provide.

OK, so say you can do both of those things across multiple FPGAs or ASICs. And you do it at the RTL level, pre-synthesis. And, unlike DFT, you can capture not just a single-cycle pass/fail result, but also a history for backtracking how a particular state was reached. And, unlike with the ARM and MIPS debug stuff, you’re debugging not just software, but hardware at any level.

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