Have We Lost The "Wow" Factor?
At a recent semi-social, semi-business function, I was asked what I thought the highlights were in electronics in 2014. I was stumped. Not only could I not think of a highlight then, I still can not think of anything that really stuck out in the year.
I've sat through many new product presentations and press briefings and received many more press releases, and there is a lot of creative thinking and very good solid engineering going on, resulting in good solid products that are meeting customer needs. I've written about some of them and hope to write about more some time later in the year. There have also been some things that have been a complete waste of time – but I have been moderately successful in trying to wipe those from my memory.
An In-Depth Interview with Kevin Morris
Time to break out the sparklers, the bailing wire, and your best O-scope. We’re having an EE party In honor of the 50th Anniversary of Moore’s Law. In this week’s Fish Fry, we investigate how Gordon Moore's legendary 1965 article in Electronics Magazine set the stage for a remarkable half-century of innovation in our industry. We also look at how (and why) Moore's Law may not mean as much going forward as it has in the past. My guest is Kevin Morris, editor-in-chief of EE Journal. Kevin is here to chat with me about how the 50th anniversary of Moore’s Law plays into the future of electronic design, his FORTRAN days, the learning curve of FPGA design, and even a little bit about his favorite project of all time.
Saleae Logic Analyzer is a New Take on Lab Equipment
“Oh, and one more thing…”
You can almost hear the ghost of Steve Jobs introducing the Saleae Logic Pro 16, gesturing to a rear-projection screen as he slips the device out of his pocket. It’s that kind of logic analyzer.
Huh, what? Trendy, stylish, desirable test instruments?
Believe it. The Logic Pro 16 is a hardware logic analyzer that even a design aesthete would love. It’s the lab instrument for the SoHo/Noe Valley/Pearl district crowd. And I have one. And no, you can’t borrow it.
Kaufmann Award Winner Shares His Thoughts
So you’ve been toiling away in the depths of the EDA world and you are struck by an idea of monumental brilliance and potential. You drop what you’re doing and go off into a cave for a while to flesh it out to the point where you can solicit a hearty investment by a forward-thinking manager of an aggressive investment fund.
What are your chances?
It certainly won’t come as a surprise that you’ve got more than one roadblock to get by. It’s not an easy investment environment out there – for high tech in general (at least for anything you can actually put your hands on). Even tougher for EDA.
EDA Past, Present, and Future with Lucio Lanza
He's toiled at this project for years - dreamt about it, laid awake at night thinking about it, and even built a lab in his basement to test it. Eventually he brought in friends (from work mostly) to fill in the missing pieces, and before he knew it they really had something. We all know this story. It has played out time and time again. It's the story of the startup, and today's Fish Fry celebrates the men and women who work every day with innovation in their hearts and minds. My distinguished guest is Lucio Lanza, an EDA mentor, venture capitalist, and believer in startup innovation. Lucio is here to explain why funding startups is so crucial in today's EE ecosystem and where he thinks EDA is headed in the future. Also this week, we check out a brand new way to get that semiconductor quote you've been looking for without giving you a headache or breaking your fax machine.
Cell-Aware: Meet Slack-Based. And STAR: Meet eFlash.
Ah, the air has cooled. The sun lolls about at a low angle for a few tentative hours. Morning frosts seal the fate of any remaining tender plants. Here in northern Oregon, the Gorge winds blow random gale-force patterns, making it unnecessary to sweep the leaves off of the patio. And, slightly farther north, it’s ITC (that would be the International Test Conference) season, in Seattle this year.
Which means it’s the season for test announcements by EDA companies. Synopsys made some noise, but not with one big blockbuster new thing; rather they assembled a couple of newsy bits that, summed together, merit some discussion.
Just to organize my thinking here, so that I don’t get us lost, there are two basic announcements: Cell-aware+Slack-based testing and STAR for eFLASH. The first involves two subtopics that we should review first.
A Whole New Way of Switching
I love surprises like this. You go into what promises to be a wonky, even dull, conference presentation – and come out agog.
That’s exactly what happened to me at the recent ICCAD in San Jose. It was a presentation based on a collaboration between the University of Michigan, Shanghai Jiao Tong University, and National Tsing Hua University about some placement or routing algorithm, but it happened to involve a transistor type that I’d never heard of. And… I don’t know, there was something about the regularity of it, perhaps its elegance, illuminated through a very lucid presentation, that caught my fancy. Heck, even with no prior knowledge, I could actually follow most of the talk. That was exciting enough. Great success!
So… what was this thing? It was a way of implementing logic on a fabric of single-electron transistors (SETs). In fact, a reconfigurable fabric. This could be your new FPGA some years hence. But, while I could follow the logic of the presentation, I had no idea what a SET was, nor did I understand why certain constraints existed that affected the algorithms presented.
Calypto’s Catapult 8 Takes Us Higher
Bob killed the headlights and put the car in park. We sat in silence. Eerie lights danced on the horizon. First east, then west, and then straight up into the night sky. We watched with mouths agape as the lights came closer (and closer), only to quietly fade away. A UFO in our midst? Not quite. HLS. Most of us have been watching the skies in hopes for the arrival of High Level Synthesis for years. Steering today's HLS-powered flying saucer is my guest Mark Milligan (Calypto Design Systems). Mark is here to reveal the mysteries of Catapult 8. He'll shine a light on how HLS is powering image processing and video applications, and explain how we can get to design closure from the top or the bottom. Also this week, we introduce a kickstarter campaign that aims to bring fashion-forward wearable fitness monitors to your next holiday wish list.
Separate Flows Target Software and Hardware
The problem... is you.
I know, it seems a bit harsh, blaming FPGA designers for restricting the expansion of the FPGA market. After all, FPGA designers are the fans, right? We are the loyal, the ones who have supported the technology all these decades, the ones who have toiled and struggled and applied our customer-side creativity to help solve the myriad challenges associated with getting one of the coolest and oddest chip architectures ever invented to behave well enough for actual system use.
Are You Ready for Tomorrow?
There are times when you shouldn't really think too deeply about things. Last week I was driving along the motorway from London to Winchester. While accelerating to overtake, I saw the engine pass through 4,000 rpm, and I wondered about each piston moving from stationary at top dead centre to stationary at bottom dead centre and then back to top dead centre 50 times a second. (Geeky? Moi?) Sadly, I can't perform in my head the sum that would calculate the speed at which each piston was moving at its fastest, but it must be pretty speedy, and that cycle of movement would be putting all sorts of stresses on all sorts of metal parts. I eased my mental stress by consoling myself that, at least in my 15-year-old Golf, there wasn't software running on silicon to control the engine.
So I didn't have to worry that the software could be like that in the Toyotas that may have suffered unintended acceleration. There has been no resolution on whether the software caused the issue. The evidence of software guru Michael Barr was so damning that, while he couldn't say that the software caused the incident, he had the Toyota lawyers worried. Add to this the way in which the opposing legal team were being successful in throwing dust into the eyes of the jury and sowing doubt into their minds, and it is clear why Toyota settled out of court.
Carbon Design Systems Announces the Carbon System Exchange
So I hear you’re going to try to build an SoC. Good luck; you’ve got lots of work ahead.
First you have to come up with an architecture. Then you need to design all of the blocks yourself. Then you need to write all of the software that’s going to run on this beastie. By yourself.
That’s the easy part. When you’re done with that, you have to verify the whole thing. Yes, you have to design everything and finish it all before you can start your verification. I just hope you don’t make any mistakes at the early architecture level.
So, okay then, off you go like a good lad.
To Grandma's PCB We Go
This week’s Fish Fry is all about your next PCB design. From power integrity to mixed-signal place and route, from Gerber files to schematics, from output pins over the FR4 and through the vias, to grandma’s house we go. My first guest this week is Greg Lebsack from Tanner EDA, and we discuss why you want a digital place and route tool, integrating ye ol’ analog into your next design, and what Tanner EDA brings to the mixed-signal party. Next up, we bring in Hemant Shah from Cadence Design Systems to chat about one of the biggest pain points of PCB design: the hand off to manufacturing. Hemant and I investigate a rapidly expanding industry consortium that is hoping to change all of that awful file hand off once and for all.
Or, How the Heck Do I Design a Photonic Circuit?
Several weeks ago we took a look at the expanding role of EDA. And then a couple weeks ago we delved into the bizarre world of silicon photonics. Yeah, we didn’t get too deep because the bottom drops off pretty quickly, and I’m not sure I could tread water credibly any deeper. But we got a flavor.
So now, we bring these two things together to answer the question, “If I’m going to be involved in a photonic chip design, what tools am I going to use?” OK, so if you’re an electronics designer, you’ll probably be asking the question, “What tools will the photonics pholks be using, and how will thier world interface to mine?”
Folks have been doing silicon photonics research for a long time now, and you need tools to do that. So it’s not like we’re just now seeing the emergence of new tools for this purpose. The thing is, there’s not a lot of profit in research, so the big guys that are commercially driven may not be attracted to such new endeavors in the early stages.
Carbon’s New Virtual Prototype Portal and UDG’s New Smart Robot
What’s the difference between a human and a pile of rocks? A robot algorithm (of course)! In this week’s episode of Fish Fry, we check out a new robot being developed at the University of Guadalajara that utilizes a pattern recognition algorithm to determine the silhouette of a human body. Also this week, we talk about the trials and tribulations of SoC design with Bill Neifert of Carbon Design Systems. Bill and I discuss Carbon's focus on the automatic creation of RTL-accurate models for integration into SoC designs and how you can make your IP configuration options a whole bunch easier.
Newer Tools Let You Do More than Just Electronics
Welcome to autumn. It’s usually a busy season – although the activity typically starts more with the onset of September and the resumption of school than with the equinox. But it also comes on the heels of a quiet season, even in the overworked US.
And EDA has seemed moderately quiet. So I started looking around to see what I might have been missing, and I’m not sure there’s a lot. But it did get me musing on why things might be quiet for the moment as well as what fills the gap – which gets to the topic of what qualifies as EDA. It’s more than you might think.
At the risk of being obviously over-simple, the legions of coders in EDA-land are doing one of two things: building new technologies or improving on old ones. The new technology category might include support for FinFETs or multi-patterning or the design kits for the latest silicon node. The improvement side of the tree is where performance and capacity and usability are juiced up – all in the name of productivity, of course.