FPGA Cores for SoC Designers
Since 2013, Achronix has been cruising along, quietly doing a decent business with their Speedster FPGA family. Their particular value proposition resonates well for certain networking and acceleration applications, and they’ve mined a good business by strategically poking at gaps in the Xilinx and Altera product offerings in certain markets. More recently, their Accelerator-6D PCIe board - bringing FPGA-based compute acceleration to existing server installations - has gotten good reviews.
Zeno Claims Double the Drive, No Extra Leakage
You may remember that, early this year, we took a look at a 1-transistor (1T) SRAM bit cell. (Yes, new memory stuff seems all the rage lately – and we’re probably not done yet.) Well, there’s another story evolving out of that 1T cell, only it’s not related to memory. It’s related to one of the most fundamental devices in our toolkits: the transistor itself. Zeno claims that they can boost the drive current of an ON transistor by two times – something that would ordinarily take several process nodes to achieve. And all without increasing leakage – something several process nodes would not likely be able to provide.
They call it βMOS, with “beta” standing for “boosted.” And they found it more or less by accident while characterizing their 1T bit cell. So let’s start by reviewing that cell.
Why Not Open Source?
Wouldn’t it be great if there were more options in FPGA tools? For decades now, the FPGA community has decried the lack of FPGA design tool options. You’d think that a technology that has been evolving and maturing for over thirty years would have long ago reached the point where there were a wide variety of competitive programming options to choose from. However, we are still basically at the point where there is one and only one option for doing your FPGA design - the tool suite sold and distributed by the FPGA company itself.
It’s not that the third-party and open-source communities haven’t tried to find ways to produce viable alternative design flows. They have. Numerous EDA companies, from fast-moving, highly-motivated, innovative startups to big lumbering institutionalized EDA vendors have poured creativity, energy, determination, and piles of cash into efforts to build a third-party ecosystem for FPGA design. Well-minded communities have unleashed proven formulas for open-sourcing solutions to complex problems, looking for an alternative to proprietary tools. All to practically no avail.
Write Once, Use Many
Noooooo! Are you kidding me? How many times has this happened so far? You know tape-out is tomorrow, right? Dangit!
The New Showdown in Programmable Logic
Sunday! Sunday… SUNDAY! Get your tickets now! Fire-breathing System-in-Package FPGAs square off in a duel for the ages! See Xilinx’s FinFET-powered 16nm TSMC-fabbed UltraScale+ Virtex and Zynq take on Intel’s new Altera-powered Stratix and Arria Generation 10 SoC FPGAs and SiPs. Watch Quartus and Vivado spar for design tool supremacy! Feel the heat as distributors such as Avnet, Arrow and others pile on legions of FAEs armed with development kits, reference designs, and IP blocks in winner-take-all battles for dominance in communications, data center, automotive, industrial, and IoT applications. That’s right, we’ll sell you the whole socket, but you’ll need only the edge.
Drones, Formal Verification, and A Move Toward System C
In this week’s Fish Fry, we look to the skies for the next big thing in verification technology - formal verification. Dave Kelf from OneSpin joins us to discuss the past, present, and future of formal verification, what formal does that simulation does not, and details of OneSpin’s “Game of Drones” contest. Then, in keeping with our airborne theme, we take a closer look at a new drone called “Deep Purple” developed by the US Army's Edgewood Chemical and Biological Center - designed specifically to sniff out biological and chemical agents in the air.
Mentor Discusses DRC’s Newer Cousin
When you look at someone’s face, what do you see?
I suppose that depends on who you are. Many people are good at picking up the details. Eye color is a big one that can sometimes get you in trouble if you don’t catch it. Other people aren’t so big on the details, but they can generate overall impressions based on a “look.” Your intrepid reporter would place himself in the latter category – seeing similarities in looks between people that others don’t see at all while missing the eye color.
At the risk of a neck-jarring change of direction here, let’s take this into EDA – and, in particular, the art and science of proving that a particular layout will work and yield. This is the realm of design-rule checks (DRC). But DRC is somewhat like noticing eye color: it’s focused on very specific detailed dimensions (or small collections of dimensions).
Adventures in FAST Spice and Secret Message Jelly Fish
What do SPICE and a new material inspired by the skin of squid and jellyfish have in common? This week's episode of Fish Fry of course! First up, Zhihong Liu, Chairman and CEO of ProPlus Solutions joins us to discuss trends in the SPICE world, the challenges of displacing circuit-level FastSPICE simulators, and why he thinks table tennis is the best sport in the world. In the second half of our episode, we investigate a new type of material inspired by the reactionary skin of squid and jellyfish developed by a team of researchers at the University of Connecticut. This newly developed material may change how we interact with our cellphones, how we trade in our electronics, and how we send (secret) messages as well.
The Intel/ARM Agreement is a Smaller Deal Than It Sounds
You don’t often see the names “Intel” and “ARM” used together in a sentence without words like “rival” or “competitor” in between them. They’re like oil and water, cats and dogs, Dodgers and Giants.
But, just this week, we saw the lion lie down with the lamb. What’s this? Intel and ARM are working together? Intel will be making ARM processors? It’s the end of the world as we know it!
How is Your Register Behaving?
Registers: It’s a dirty job but someone has to do it. In this week’s Fish Fry, we take a closer look at register behavior modification and sequence automation with Anupam Bakshi of Agnisys. Anupam and I also discuss design intent and the future of verification intent. Whether we like it or not, we all need a little help sometimes, right? In the second part of our EDA special, we welcome Bob Smith from the Electronic System Design Alliance. Bob and I discuss how the ESDA is helping facilitate IP fingerprinting and 3D system scaling, as well as bridging the gap between hardware and software in embedded system design.
Expediting System Design
Respin! Respin! Respin! Are you afraid yet? For three decades, the electronic design automation (EDA) industry has relied on that fear. They learned way back in the 1980s that the quickest path to the biggest budget when selling software tools was through fear of the dreaded, career-limiting IC design respin. Want to sell me something that makes my engineers more productive or my designs more optimal? Meh… Maybe. Want to sell me something that prevents me from taking the blame for a respin on my project? How much money do you need?
SiFive Leverages Open-Source RISC-V for Customizable Compute Platforms
Makers are the epitome of what big chip vendors used to consider a waste of time for their valuable salesfolk. “Fred in the shed,” as they said. No volume, no ROI. “Stick with Tier 1s.”
But you Makers are now in demand, given that you’re particularly good at things required for Internet of Things (IoT) types of systems, taking readily-available platforms and making them do cool things – things that larger companies are now more interested in; things that could potentially sell in high volumes. I don’t know whether chip guys are now selling to Makers, but Makers have definitely been courted with more platforms (hardware and software) and tools for getting, at the very least, proofs of concept out the door quickly.
What’s Next After Moore’s Law
The EDA industry has always been a bit of an enigma. On one hand, EDA has provided the essential technology that has enabled Moore’s Law to proceed for half a century. Without the incredible accomplishments of EDA’s engineers, today’s multi-billion transistor marvels would never have had the chance to exist, and their world-changing capabilities would never have seen the light of day.
Yep, that’s right. I’m saying that without EDA we would not have Pokemon Go.
IoT, FinFETs, and the Tools We Need
The air is a perfect 72 degrees. The water is calm for now, but breakers dot the horizon. The time for the next mondo wave isn't here now, but it will be soon. In this week's fish fry, we're surfing our way to the next big computational wave with a little help from David Dutton (CEO - Silvaco) and Lisa Minwell from eSilicon. David and I discuss why we will see a lot more design requirements coming out of middle nodes, why on-board power will be more important than ever before, and a little bit about why our design tools will be the key to our future success in IoT. In the second half of our episode, Lisa Minwell and I chat about the components of a successful IP company and where 2.5D (and 2.1D) designs will find their foothold in the future.
ProPlus Claims to Do Full SPICE Faster than Fast
Years ago, my brother was visiting relatives in Austria. As the story goes, the family was aristocratic once upon a time, and, while that didn’t devolve into riches and status (or even awareness of that fact) for my family, it was still part of the relatives’ mindset. Which gave them a sense of entitlement and “natural” superiority.
So when my brother was describing the California climate, within which he had lived for most of his life, and where you go from, oh, say, April through October without rain – a climate distinctly different from central Europe, he got a simple response: “Not possible.” And that was that. No amount of data or convincing would get them to believe such nonsense.