Cadence Launches Innovus
It’s a familiar tale of woe: new silicon process nodes are creating an extreme burden for design tools.
When I say, “familiar,” it’s not just because everyone is bemoaning the current state of affairs, what with FinFETs and multiple patterning and other new features creating innumerable vexations. No, it seems that this happens after every few advances: the improvements made to nullify the last set of hurdles run out of steam in the face of the latest set of new hurdles. And so tools get rolled again.
The product of the tools – a correct mask set – hasn’t changed; the ways we get to that mask set have changed over and over. And continue to do so.
Taming the Wild West of EDA Design with OneSpin
This week we’re saddling up and taking a ride into the Wild West, where the days are long and the code is even longer. We’re talking about the rough and tumble, SystemC slingin’, HLS wranglin’ assertion-based formal verification. Dave Kelf (OneSpin Solutions) rides with us across the dusty EDA plains of RTL design where we unveil why RTL (and above) is called the Wild West of Design, who exactly is playing sheriff in these here parts, and how design and verification at the RTL level can be corralled once and for all. Also this week, we address the most recent rumors surrounding the Intel/Altera buyout deal and investigate the newest (and coolest) smartwatch this side of the Mississippi - an Enigma machine for your wrist!
Cadence Stratus Ushers In a New Era
It’s been more than twenty years since I started working on high-level synthesis (HLS). You might say I’ve studied the topic a lot. For most of those two-plus decades, HLS has been widely considered the “design methodology of the future.” And there are those who have held onto the belief that it always will be.
For those of you not in tune with the terms, high-level synthesis is the automatic creation of hardware architectures from behavioral descriptions. At first, HLS was known as “behavioral synthesis.” But, after some early bad experiences, the EDA industry quietly shifted the name over to HLS - hoping that nobody would notice or have episodes of PTSD when confronted with the idea.
Altium Brings the Goods to Makers, Startups, and Engineers Alike
Buying PCB software can be a lot like purchasing a new car. Once you've got the full set of amenities that you've always wanted (don't forget the TruCoat!), you're about ready to take out a second mortgage on your house. PCB design software does not have to break the bank or cause ruffled feathers during your next budget review. In this week's Fish Fry, we examine the multiple flavors of Altium's PCB tool suites packages -- all the bells and whistles, price points, and more with Sam Sattel, PCB rockstar from Altium. Also this week, we check out iSkin - the newest research in wearable technology coming out of the Embodied Interaction Group in Germany. You won't want to miss it!
Synopsys Shrinks an NVM Cell
Memory comes in many flavors. That’s because it’s used for so many different things, and requirements vary widely. We’re used to DRAMs, which we need to be able to get at often and quickly, and we’re used to FLASH, which needs to keep its contents after the power is turned off.
But there is other usage to be found on the other end of the volatility spectrum. At the far end is “one-time programmable” memory – OTP. For instance, if you use memory bits to store calibration information or to trim in some parameter, then, assuming you won’t have to account for aging in the future, you set it once and you’re done. You’ll never need to (or be able to) reprogram that again. Think antifuses and such.
Giving a Voice to Your Abode with Conexant’s Smart Home Technology
When you think of a smart home, what comes to mind? The Jetsons? A Ray Bradbury novel? The "Clapper" perhaps? In this week's Fish Fry, we investigate one of the biggest technological trends in IoT: Smart Home Automation. My guest is Saleel Awsare from Conexant. Saleel and I explore how voice control technology will shape the smart home revolution, and we look into the challenges of creating a voice-controlled Smart Home. We also speculate a bit about the direction voice control software is headed. Also this week, we check out how FPGA technology can lend a very valuable hand in your next USB Type-C design.
The Next Big Thing?
The scene: A hotel breakfast room. There are several groups, mostly of men wearing the same logo-marked polo shirt, or matching ties, speaking English and having breakfast. Out of one group comes, "Their BIOS was rubbish, so we had to write a completely new one." Welcome to Nuremberg during embedded world.
For three days all the hotels are packed, despite having doubled their room rates. The U-Bahn (Metro) adds extra services from the city centre to the Exhibition site, and over 900 exhibitors are visited by more than 20,000 people. Amongst them are the editors, rushing around to their long list of press conferences and press briefings. During three days I spoke to around 4% of the exhibitors in formal meetings and a few more in informal sessions. I also received many, many press releases associated with products being launched at the show. (As I write, my inbox is being flooded with Mobile World Congress releases - in fact, so many, they are even overtaking the spam.) What follows is my attempt to capture the main trends in embedded systems based on those meetings and on the way in which companies were branding their booths.
Putting Your Tools Where Your Mouth Is
Breaking into any part of the FPGA market ecosystem is a substantial challenge. Countless companies have launched with various novel ways to take advantage of FPGA technology, and the countryside is littered with the carnage of their decaying carcasses. It’s not a friendly environment out there in FPGA land.
Ironically, the biggest danger for FPGA startups is the FPGA companies themselves. Their track records over the past couple of decades have established them as shining examples of the “frenemy” concept. In order to succeed in FPGAs, you have to partner with the FPGA companies. Then, at some point, you generally find yourself competing with them in one way or another - usually by trying to sell tools or IP that they give away for free.
Unveils New 16nm UltraScale+ Families
When the #1 FPGA company makes what is arguably their biggest new-technology announcement in a decade, you’d expect there to be a lot of substance. With this week’s announcement of UltraScale+ Virtex, Kintex, and Zynq devices planned to roll out on TSMC’s 16nm FinFET process, the company did not disappoint. This is one of the broadest, most complex announcements we have ever heard from Xilinx. So, with that preface, let’s take a look at what those folks on the south side of San Jose have been up to lately.
In summary, Xilinx is announcing new Virtex, Kintex, and Zynq families of programmable devices with major improvements in capability over previous generations.
Design Verification’s Party of the Year and Supply Chain Risks We Should Avoid
In this week’s Fish Fry, we’re serving up a virtual smorgasbord of EE goodness! First up, it’s a trip to the global supply chain salad bar with Lynn Torrel from Avnet. Lynn and I dig into the biggest trends driving the global supply chain, the challenges of multi-dimensional supply chain security, and which supply chain risks you should take head on. Our next guest is Yantin Trivedi who’s here to spill the beans on this year’s biggest design verification party - DVCon 2015. Finally, we round out our scrumptious EE feast with a look into how we can banish the ugly mixed-signal verification monster once and for all.
Full Production on High-Performance FPGAs and Tools
Few challenges in the world of high-technology startups are as daunting as that of putting a new FPGA company on the map. Sure, there’s the obvious hurdle of coming up with a better mousetrap - against two extremely innovative and experienced mousetrap makers who most certainly have deeper pockets than you. And deep pockets matter. If you don’t have the resources to deal with the nine-digit-dollar entry fee for new device development at competitive process nodes, you’re better off not leaving the starting line.
Then, there’s the matter of timing the waves. Let’s say you came up with a fancy new FPGA design, and you planned to implement it at 28nm. If you started designing at about the time 28nm technology was first available, and you executed your design project perfectly, you’d at least be on an even playing field with the big established companies. (Not that the even playing field would help that much, given that the other teams have about 50x the number of players you’re fielding.) But chances are, you didn’t execute your design project perfectly, and chances are, the semiconductor fab didn’t give you top priority compared with their long-time high-paying partners. That means you launched your 28nm a year or so later than the big guys.
Without Competing With the Big Guys
So your company needs to design a system-on-chip (SoC). On the one hand, there’s a lot of that going around. On the other hand, the cost of doing an SoC – especially on an aggressive silicon node – is so expensive that the number of companies that have the cash to do that is decreasing.
Which limits the number of competitors to a certain degree. But you’re still going to have competitors. How are you going to make sure that, when system builders are looking for an SoC, they choose yours?
That’s how a standard product marketing discussion might go, but things can work differently with SoCs, While you might find merchant-market SoCs for, say, a communications protocol like Bluetooth or for power management, many SoCs are created by, or on spec for, system builders, so presumably the feature set has been tuned to be exactly what the system needs. So, really, it’s the system architects that are defining the differentiating aspects of the system, and the SoC is “merely” an implementation of those features.
Radio Shack Goes From 50-in-1 to None
My fingers trembled and my heart pounded. I carefully bent spring terminal #35 and inserted the tinned end of the final wire. I was confident that I had double-checked every connection, but I still felt unsure.
As I slowly turned the knob labeled “variable condenser,” I thought I heard a hiss or some static. Then, suddenly, Merle Haggard singing “Branded Man” boomed through my tiny earphone. I jumped! I couldn’t believe what I was hearing. I hated country music, and it was the most beautiful sound my seven-year-old ears had ever heard.
Prototyping MATLAB and Simulink Algorithms on Xilinx Zynq and Altera SoCs
The year 2011 saw a signature development in the FPGA industry – the introduction of two new programmable SoC devices. Xilinx introduced the Zynq-7000 All Programmable SoCs, and Altera introduced the Cyclone V SoC and Arria V SoC FPGAs. These new programmable SoCs, each packing a high-performance dual-core ARM Cortex-A9 MPcore along with ample amounts of programmable logic, offered advantages for a plethora of applications. Now designers could enjoy the benefits of software application development on one of the industry’s most popular processors while gaining the flexibility and throughput potential from hardware acceleration on a high-speed, programmable logic fabric.
The concept of designing, validating and then reusing functional blocks in integrated circuits (ICs) has been entrenched in the electronics industry for decades. Software development has a similar model utilizing libraries of common function calls or objects. However, the concept of reusing printed circuit board (PCB) modules is much less common. Reusing PCB modules for common or commodity functions offers considerable advantages, for example avoiding potential signal integrity or thermal problems, by utilizing circuit data whose performance has been proven in previous generations of products. The key to successful modular circuit design is a data management system that can store and control access to modular reusable blocks, manage information that is critical to design reuse, such as the layer structure of a routed block, and interface easily with the circuit design software. The end result is a reduction in time during schematic capture and PCB design, along with fewer design errors, making it possible to bring quality products to market faster.