Altera Turbos the Tools

Spectra-Q Accelerates Quartus II

by Kevin Morris

When people are curious about the performance and capabilities of programmable logic products, they often get buried in the details of the datasheet. It’s easy to get wrapped up in debating LUT counts, Fmax numbers, and a bunch of other silicon-related esoterica that may have little to do with how well a particular device will perform in your application.

You know what matters a lot more than the details of the chips? The performance of the tools.

The under-appreciated universal truth of programmable logic is that tools usually have a lot more to do with the success of your design than the silicon does. Luckily, even though the customers don’t always understand this, the vendors certainly do. Altera and Xilinx each spend a substantial share of their engineering budgets developing and improving their tools in order to gain a competitive advantage and make their customers more successful with their devices.

 

Faster Extraction

Mentor’s xACT Wrestles with FinFETs, Corners

by Bryon Moyer

So you build a circuit with a couple of transistors here and a couple of transistors there and you want to see how it’s going to operate. So you’ll simulate (or do signal integrity analysis or whatever other study you’re interested in). But you need to tell the tool about your circuit. So… do you just say, “Yeah, I’ve got a couple transistors here and a couple resistors there – please go calculate”?

Ah, if only it were so simple. Of course that won’t work – because it ignores all of the unstated interactions between the elements and other parasitic structures in the silicon substrate. Back when circuits were small, that meant manually building a more complete model that included the extra resistors and capacitors (and perhaps the occasional inductor) and putting that whole thing through the tool.

 

Paint It DAC

2015 Design Automation Conference Preview

by Amelia Dalton

It's that time of year again. Ring the bells, sound the alarm, and roll out the red carpet - it's DAC time! In this week's Fish Fry, Anne Cirkel (General Chair - DAC 2015) gives us a special sneak peek into the biggest EDA conference of the year - The Design Automation Conference. Anne dishes the details of the conference: the super cool keynotes, the "I Love DAC" program, and the inside info on the best parties at this year's show. Also this week, we examine a unique Kickstarter campaign that marries nanotechnology with fashion to create this season's must have: The Unstainable™ White Shirt.

 

Changing the PCB Axis

Mentor PADS Redefines the Board Genre

by Kevin Morris

Anybody who has ever bought professional PCB software has probably noticed a problem with the way PCB tools have always been packaged, priced, and marketed. Well, anybody except for the folks who actually sell PCB tools, that is. For some reason, PCB tools have always been sold with a built-in wrong assumption - that only big companies with large design teams are doing sophisticated designs. If you were a huge company with giant design teams that required all the “enterprise” features related to team design, collaboration, IP sharing, and library management, the PCB tool vendors gave you all the features needed for leading-edge, high-performance board design.

But, if you were a smaller company or team who didn’t require all the big collaboration features, you got the toy-like “desktop” PCB tools which didn’t include the stuff you needed for high-performance, high-density board design.

 

Cramming Moore Components

Moore’s Law Turns Fifty

by Kevin Morris

It’s been a half-century since Gordon Moore published “Cramming More Components Onto Integrated Circuits” in the April 19, 1965 edition of Electronics Magazine. It was another five years before Carver Mead dubbed Moore’s prediction in that article - about progress in integrated circuit density - “Moore’s Law,” and another five years after that before Moore revised his original “doubling every year” prediction to “doubling every two years.” At its simplest level, then, Moore’s Law predicts that the number of transistors that can be fabricated on a single chip will double every two years.

The fifty years that have followed that prophetic piece have seen nothing short of the most amazing advances in human history. Moore originally predicted that the trend would continue for “at least ten years,” but the exponential he foresaw has held almost miraculously steady for five times that long. Some would say that Moore brought incredible insight with his prediction. Others would say he was lucky. Still others would claim that this is an example of self-fulfilling prophecy. Whatever the case, the profound impact of that one metric - “number of transistors on a single chip” - on just about every aspect of our global society is almost unfathomable.

 

ARTEMIS is Dead – Long Live ECSEL

The changing role of European Funding for Embedded Systems R&D

by Dick Selwood

The European Union (EU) is a complicated beast. It isn't a United States of Europe, although in some lights it can look like it, as it has laws that overrule those of member states, and it uses a common currency (although not all member states use the Euro).

Its roots are in the devastation of the Second World War, when a shattered Europe was rebuilding its industrial base and at the same time looking for ways to ensure that there would never again be conflict between European countries. It has been successful in both those aims and has taken on increasing powers as it has expanded to include 28 countries. It is now a single market with no customs duties or protectionist measures and, with the addition of Switzerland, Norway and some "micro states" like the Vatican, is a passport free area, except for the Republic of Ireland and the United Kingdom. One task of the EU is to improve the competitive position of European industries, particularly those that are seen as important to future growth, such as electronics.

 

Revamped Digital IC Flow

Cadence Launches Innovus

by Bryon Moyer

It’s a familiar tale of woe: new silicon process nodes are creating an extreme burden for design tools.

When I say, “familiar,” it’s not just because everyone is bemoaning the current state of affairs, what with FinFETs and multiple patterning and other new features creating innumerable vexations. No, it seems that this happens after every few advances: the improvements made to nullify the last set of hurdles run out of steam in the face of the latest set of new hurdles. And so tools get rolled again.

The product of the tools – a correct mask set – hasn’t changed; the ways we get to that mask set have changed over and over. And continue to do so.

 

RTL Roundup

Taming the Wild West of EDA Design with OneSpin

by Amelia Dalton

This week we’re saddling up and taking a ride into the Wild West, where the days are long and the code is even longer. We’re talking about the rough and tumble, SystemC slingin’, HLS wranglin’ assertion-based formal verification. Dave Kelf (OneSpin Solutions) rides with us across the dusty EDA plains of RTL design where we unveil why RTL (and above) is called the Wild West of Design, who exactly is playing sheriff in these here parts, and how design and verification at the RTL level can be corralled once and for all. Also this week, we address the most recent rumors surrounding the Intel/Altera buyout deal and investigate the newest (and coolest) smartwatch this side of the Mississippi - an Enigma machine for your wrist!

 

HLS is the New Black

Cadence Stratus Ushers In a New Era

by Kevin Morris

It’s been more than twenty years since I started working on high-level synthesis (HLS). You might say I’ve studied the topic a lot. For most of those two-plus decades, HLS has been widely considered the “design methodology of the future.” And there are those who have held onto the belief that it always will be.

For those of you not in tune with the terms, high-level synthesis is the automatic creation of hardware architectures from behavioral descriptions. At first, HLS was known as “behavioral synthesis.” But, after some early bad experiences, the EDA industry quietly shifted the name over to HLS - hoping that nobody would notice or have episodes of PTSD when confronted with the idea.

 

32 Flavors of PCB Software

Altium Brings the Goods to Makers, Startups, and Engineers Alike

by Amelia Dalton

Buying PCB software can be a lot like purchasing a new car. Once you've got the full set of amenities that you've always wanted (don't forget the TruCoat!), you're about ready to take out a second mortgage on your house. PCB design software does not have to break the bank or cause ruffled feathers during your next budget review. In this week's Fish Fry, we examine the multiple flavors of Altium's PCB tool suites packages -- all the bells and whistles, price points, and more with Sam Sattel, PCB rockstar from Altium. Also this week, we check out iSkin - the newest research in wearable technology coming out of the Embodied Interaction Group in Germany. You won't want to miss it!

 

Midrange Embedded Memory for Analog

Synopsys Shrinks an NVM Cell

by Bryon Moyer

Memory comes in many flavors. That’s because it’s used for so many different things, and requirements vary widely. We’re used to DRAMs, which we need to be able to get at often and quickly, and we’re used to FLASH, which needs to keep its contents after the power is turned off.

But there is other usage to be found on the other end of the volatility spectrum. At the far end is “one-time programmable” memory – OTP. For instance, if you use memory bits to store calibration information or to trim in some parameter, then, assuming you won’t have to account for aging in the future, you set it once and you’re done. You’ll never need to (or be able to) reprogram that again. Think antifuses and such.

 

If You Build It

Giving a Voice to Your Abode with Conexant’s Smart Home Technology

by Amelia Dalton

When you think of a smart home, what comes to mind? The Jetsons? A Ray Bradbury novel? The "Clapper" perhaps? In this week's Fish Fry, we investigate one of the biggest technological trends in IoT: Smart Home Automation. My guest is Saleel Awsare from Conexant. Saleel and I explore how voice control technology will shape the smart home revolution, and we look into the challenges of creating a voice-controlled Smart Home. We also speculate a bit about the direction voice control software is headed. Also this week, we check out how FPGA technology can lend a very valuable hand in your next USB Type-C design.

 

Safety 'n' Security

The Next Big Thing?

by Dick Selwood

The scene: A hotel breakfast room. There are several groups, mostly of men wearing the same logo-marked polo shirt, or matching ties, speaking English and having breakfast. Out of one group comes, "Their BIOS was rubbish, so we had to write a completely new one." Welcome to Nuremberg during embedded world.

For three days all the hotels are packed, despite having doubled their room rates. The U-Bahn (Metro) adds extra services from the city centre to the Exhibition site, and over 900 exhibitors are visited by more than 20,000 people. Amongst them are the editors, rushing around to their long list of press conferences and press briefings. During three days I spoke to around 4% of the exhibitors in formal meetings and a few more in informal sessions. I also received many, many press releases associated with products being launched at the show. (As I write, my inbox is being flooded with Mobile World Congress releases - in fact, so many, they are even overtaking the spam.) What follows is my attempt to capture the main trends in embedded systems based on those meetings and on the way in which companies were branding their booths.

 

Plunify’s FPGA Proof Point

Putting Your Tools Where Your Mouth Is

by Kevin Morris

Breaking into any part of the FPGA market ecosystem is a substantial challenge. Countless companies have launched with various novel ways to take advantage of FPGA technology, and the countryside is littered with the carnage of their decaying carcasses. It’s not a friendly environment out there in FPGA land.

Ironically, the biggest danger for FPGA startups is the FPGA companies themselves. Their track records over the past couple of decades have established them as shining examples of the “frenemy” concept. In order to succeed in FPGAs, you have to partner with the FPGA companies. Then, at some point, you generally find yourself competing with them in one way or another - usually by trying to sell tools or IP that they give away for free.

 

Xilinx Throws Down

Unveils New 16nm UltraScale+ Families

by Kevin Morris

When the #1 FPGA company makes what is arguably their biggest new-technology announcement in a decade, you’d expect there to be a lot of substance. With this week’s announcement of UltraScale+ Virtex, Kintex, and Zynq devices planned to roll out on TSMC’s 16nm FinFET process, the company did not disappoint. This is one of the broadest, most complex announcements we have ever heard from Xilinx. So, with that preface, let’s take a look at what those folks on the south side of San Jose have been up to lately.

In summary, Xilinx is announcing new Virtex, Kintex, and Zynq families of programmable devices with major improvements in capability over previous generations.

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