Mentor Upgrades HyperLynx
These days, the metal on your PCB has to do a lot more than just connect a few dots. With the pervasiveness of high-speed serial interfaces and other signals that put a premium on signal integrity (SI), most board designs can’t get away with simple-minded placement and routing anymore. And, with the compression and perforation of power planes, we can’t take power integrity (PI) for granted either.
The situation is only getting worse. New protocols and standards for high-speed interfaces like DDR4, multi-gigabit Ethernet, and PCI Express put even more strain on the design, and continually increasing operating speeds combined with decreased voltages up the ante yet again. It is becoming rare for a design team to be successful with a leading-edge PCB without state-of-the art SI and PI simulation and analysis.
MATLAB Upgrades Boost Design Creation
“Verilog and VHDL are the most natural and efficient ways for me to express my design intent.”
— No one. Ever.
Whether we’re doing FPGA or ASIC design, or programming the latest DSP, most of us don’t start out our project with regular hardware description languages. In fact, if we’re developing or tuning an algorithm, or if we’re somehow applying math to our problem, a great many of us do the early work in MATLAB. It makes sense. For translating mathematical ideas into specific algorithms, and verifying the performance of those algorithms on early data sets, MATLAB is worlds more productive than jumping straight into the design of hardware, or even into C/C++ coding.
Next-Generation DfT in Cadence’s Modus
If you’ve ever digitized your vinyl albums, you know that you have a decision to make: what format should be used to store the music? There are lossless formats like wav and flac, but they take a lot more space. Mp3 is much friendlier to your small, limited-memory listening gadget, but you lose something in the translation. It’s lossy, so the space savings come at a price. Whaddaya gonna do?
Turns out that there’s a similar problem with chip test circuits. It’s not the only problem, but compression-vs.-loss is an issue that Cadence claims to have, well, not solved (it’s never completely solved until it’s lossless and small), but improved. As a result, they’ve announced a new Modus tool for this new approach to chip testing. (Yes, another tool name ending with “-us.” I just hope they don’t do a tool that flattens out hierarchy…)
An Environment of Their Own
Want to feel old?
Wait… hello? You still there?
OK, whew… I thought you’d already answered, “No” and moved on to something else. Guess I should vet my questions more carefully.
Here’s the deal: HSPICE is 35 years old. I know… I probably should have given you time to pour a drink. I mean… I was running SPICE before there was an HSPICE. (Barely…)
(Takes a few gentle rocks in the chair…)
The New Era of Design Verification
Can you imagine a world without mistakes? Maybe it would be cool, but most likely it would be pretty boring. Heck, it might even mean some of us would lose our jobs. This week’s Fish Fry, we visit a conference dedicated to engineering mistakes: DVCon. We investigate three major the themes of this year’s Design Verification Conference: UVM, emulation, and FPGA-based prototyping. Shishpal Rawat (Chairman - Accellera Systems Initiative) and I sit down to discuss the importance of standardization in emulation and UVM, the value of design verification tutorials, and why verification needs to happen at many different levels of abstraction. Also this week, we check out the advantages of an integrated prototyping solution which may just put ad-hoc FPGA-based physical prototyping out of business once and for all.
ANSYS Brings Mechanical and Electrical Together
ANSYS has recently released version 17 of their tools, simply referred to as ANSYS 17. The improvements they made cover a lot of ground, much of it having to do with mechanical design. Which might lead you to think, “oh, this is a mechanical tool; I can move on, since it’s not for me.” But be not so hasty: we’ll return to this in a minute.
Their theme for the release is 10x, meaning lots of things are 10x better. 10x is a convenient number (I personally think of it as a convenient threshold for how much better something needs to be to get a user to switch from something else). Again, this distributes over so many feature changes (many of them mechanical) that we could take all day chasing that angle. But suffice it to say that many of the changes aim to smooth or unify flows and, in general, save time and effort.
The Big Game that Never Ends
I’ll be the first to admit that I don’t understand cricket, but I’m told that cricket matches can sometimes run for days on end, and that it’s often unclear who’s winning until, suddenly and unexpectedly, one team meets some arbitrary victory conditions and then goes home to celebrate with a few pints. The FPGA synthesis game is a lot like that. It’s a high-stakes game with vast amounts of revenue at stake, not to mention some serious technology bragging rights, but it’s never really clear who’s ahead, who’s behind, or even what the rules were in the first place. It’s been going on that way for something like twenty years, and despite fierce competition and incredible technological advances in the tools, the scoreboard is still basically a bunch of gibberish. Nonetheless, the audience is stuck on the edge of their seats (Maybe they’ve been Super Glued there?) watching every move in this weird and wacky contest between tool nerds that have never met.
GlobalFoundries’ FD-SOI Alternative
It was the coolest transistor development in many a year. Rather than continually squishing transistor parts closer and closer together, we flipped it to vertical and celebrated the arrival of the FinFET.
Which was great: it gave us a way to keep increasing performance in many of the applications where the value lies in the speed of the circuit. But after the initial party was over and we started picking up the pointy party hats and nursing the hangovers with massive doses of ibuprofen, we started looking at the bill. FinFET is nice, but it’s also expensive. And, while we’re throwing stones, it’s also not so great for analog and RF designers based on the quantized nature of the gate. You can’t increase channel dimensions by 1.5 times; it’s either 1 or 2.
ASML’s EUV Lithography Tools Push the Boundaries of Invisible
There aren’t many industries where 15 units qualifies as “a big order.”
Battleships. Nuclear power plants. And EUV tools.
For the 14,000 employees at Dutch lithography company ASML, 15 orders for EUV tools is a big deal. Even though that number spans five years and four generations of the company’s EUV equipment, it’s still considered “volume.” Walmart they ain’t.
EUV (extreme ultraviolet) lithography is still is bit space-age and sci-fi for many chipmakers. We’ve been shining DUV (deep ultraviolet) light on our chips for quite a while now, but the limits of that technology are making themselves known.
The Nature of a Bursty Business
Those of you who have been with us a long time may well remember that our humble journal didn’t start out as EE Journal. In fact, it started as FPGA Journal, with founder Kevin Morris as chief editor, writer, cook, and bottle washer. A few years later, we added a new Embedded Technology Journal (whose current embodiment is ably managed by Jim Turley). Only several years after that did we take on IC design specifically, which is when yours truly joined the fray.
And then we opened our umbrella wider, covered more topics, and consolidated into a single EE Journal, with a number of specialized “channels” that would allow our readers to on their specific areas of interest. Out of the IC newsletter were born two channels: EDA (for the tools) and Semiconductor (for the underlying silicon technology).
Xilinx Rolls Out HLx
For more than two decades, the promise of high-level design methodologies has been dangled in front of digital hardware designers. High-level design was going to revolutionize our design process. It would make us dramatically more productive. It would make us vastly more agile and adaptable as our design requirements evolved. It would make us into Super Engineers - or it would take away our jobs.
Everyone who has designed at the register-transfer level (RTL) using hardware description languages (HDLs) such as VHDL and Verilog knows, deep down in their bones, that RTL is not the answer. The detailed, nit-picky, verbose, cryptic, architecture-specific, technology-locked nature of RTL design is almost incomprehensibly clunky. Yet, for more than twenty years, it has persisted as “the way it’s done” when designing digital hardware.
Screens Will Cooperate Rather Than Compete for the Users' Attention
What is a K or k? If you are in the world of SI units, then k is the magnitude symbol for 103 (= 1,000). In computing, we are accustomed to K meaning 1024. So when you see 4K for a video standard should you be expecting 4000 or 4096 pixels horizontally? When you visit the cinema, then the 4K projector uses 4096 pixels, but if you are buying a new television badged as 4K then you will get a screen that is only 3840 pixels wide! The new Ultra High Definition (UHD) screens that TV manufacturers want you to buy this shopping season have a screen definition of 3840 by 2160 pixels – just double the HDTV standard of 1920 pixels.
But UHD TV screens are just one part of today's multi-screen world. How many screens do you own? The man who was sitting opposite me on the train today had four on the table: two cell phones, an e-book reader and a laptop computer.
Surfing the New Innovation Wave
Consolidation, consolidation, consolidation. If you’ve been following the news in the semiconductor market this past year, you’ve seen acquisition after acquisition. There is no doubt that there is a big consolidation underway in the semi space. And consolidation is nothing new. We have watched little semiconductor companies join to become bigger and bigger semiconductor companies for years.
But this time, it’s different.
The IIC Tries to Think of Everything
Deep in the heart of Portland or Austin or Minneapolis or any of dozens of towns across the nation and the world, Makers are busily building components for the Internet of Things (IoT). Long dismissed as hobbyists unworthy of sales attention, many of these skilled designers are where the IoT rubber hits the road.
Way on the other end of abstraction, folks in the Industrial Internet Consortium (IIC) have been expending much effort trying to lay out an IoT framework that might promote interoperability and numerous other desirable traits. Many of these abstract characteristics may, at some point, be implemented in a concrete fashion by one of those engineers.
EDA, Piracy, and the Stormy Seas Ahead
Their bow shreds the digital waves like a knife. They will take no prisoners. It’s the thrill of the kill they seek and they will stop at nothing until the software is theirs. In this week’s Fish Fry, we are thwarting those dastardly cyber pirates with a mighty sword - a SmartFlow sword. Ted Miracco, CEO of SmartFlow Compliance Solutions, joins Fish Fry and we’re diving into the deep murky waters of cyber security in high tech. (I also ask him what’s it’s like to play football with Alec Baldwin!) Also this week, we check out a new retro DIY gaming system on Kickstarter called Tiny Arcade.