Sage DA Automates Design Rule Test Creation
It wasn’t too long ago that we took a look at a new tool from Sage DA that could be used to create design rules in an automated fashion so that the resulting rules will be clean and consistent. It also provided a way to iron out any ambiguities in a design rule manual.
For those of you less deeply embedded in this space, what we’re talking about here is the ability to check a new chip design’s layout to make sure it doesn’t violate manufacturing rules. In order to be able to do that, we need to have a set of rules to test whether a specific IC meets the constraints of a given process. That way you ensure that no lines are too thin or spaces too narrow. (Oi, if only it were that simple.)
A Hot DATE in Dresden
The Dresden conference centre was designed to represent a stark modern contrast to the restored Baroque buildings of the old town of Dresden. For some reason, the architects decided to build a curved building with one floor on a slope, cutting through other, flat, floors. The entrance is up a long flight of stairs, exposed to the wind and rain blowing across the river Elbe. The conference rooms are all provided with wonderful glass walls overlooking the river, which have to be blacked out if you want to be able to see the information projected onto the screen.
However, it is the the main conference venue for Silicon Saxony, a “cluster” of high tech companies ranging from semiconductor manufacturers Global Foundries and Infineon to a wide range of supporting and related businesses: over 300 companies are part of the network. And it is where, in alternate years, the academic community engaged in EDA make their spring pilgrimage to the DATE Conference.
The Dark Side of Reporting Features
Do you like to be watched while you work?
Most people don’t. There’s this fine line between making sure that stakeholders know about your progress on a project and having those stakeholders all up in your business all the time. The latter is micromanagement, and no one likes that.
More and more EDA tools are being provisioned with management and reporting features. These make it easier for you as a designer to let your supervisor or project manager know what you’ve accomplished and what remains – and you spend less time writing up those annoying status reports.
Part 2 - Mentor Xpedition
Mentor Graphics is number one in PCB design tools. They want me to tell you that. They want me to tell you that - even after reading about my disdain for marketing the market share of your product. So - there ya go. They’re number one. Why does this matter? Well, they rightfully point out that nobody ever got fired for buying the leading tool, and that EDA can be a fickle business. If an EDA tool is number one (they observe), the company selling it probably cares about it deeply and will want to go the distance to support you and make you happy. Point taken.
However, since we’re all engineers here, the thing that matters the most - by FAR - is whether the tool is robust and reliable in helping you get your engineering job done. In this case - that means helping you be as productive as possible designing the heck out of your PCB. Luckily, besides being number one, Mentor has done a very respectable job of that as well. Now, however, they think that’s not enough. They’re launching a big ’ol ambitious program to upgrade their PCB design suite - in a clear effort to fend off the similarly ambitious competitors (Cadence, Zuken, Altium, et al) who are coming full-tilt right at them.
Part 1 - Cadence Allegro TimingVision
They say timing is everything, and when designing digital electronics, “they” are absolutely correct. Unless we can get the timing right on every path in our project, we’re going nowhere fast. Timing closure runs the gamut of our engineering tasks - from the inside of our FPGAs through our boards and out into the world.
With the proliferation of high-speed interfaces into common standards like DDR, PCI and others, even “normal” PCB design can involve complex timing issues, and resolving all of them at once can be a bit like squeezing a balloon. We have paths that need to meet minimum or maximum delay specifications, groups of paths that must be equal length, differential pairs that must be routed together, and phase alignment corrections that must be applied. And, all of these need to be handled during PCB routing - at the same time that we’re struggling with things like getting from point A to point B, minimizing the number of vias and layers, navigating our way out of complex BGA pin fields, and applying our sense of aesthetics to our work.
Do Standards Always Make Sense?
Not long ago, we took a look at the issue of RTL sign-off. Within that discussion was the consideration that this might go for standardization with a body like Accellera or Si2. The issue was broached by Atrenta, but it’s also a topic that Real Intent has been paying attention to, and I had a follow-on discussion with them (one outcome of which was their response to the article).
Another outcome was to get me thinking about, or rethinking, the appropriateness of subjecting something like RTL sign-off to a standard.
I’ll do one of my usual over-simplification things now: It seems like people can be split into two groups. The larger group by far consists of those folks that simply want to get along and live their lives, and this can often be done by getting together and agreeing on how things should be done in situations where it will make things easier for everyone.
It was the best of tools, it was the worst of tools, it was the age of verification, it was the age of RTL power estimation. As we navigate through these tumultuous times of electronic design, we need a design tool compass to help show us the way and Fish Fry is here to set the course. Frank Schirrmeister (Cadence Design Systems) and I hunt for the deep dark secrets of ARM-based design verification and examine how Cadence’s Palladium Emulation system fits into the verification landscape. Norman Chang (VP - Ansys) and I dip into the murky waters of ESD and together we swim toward a new solution that can make the most troublesome paths in our designs a little easier to navigate.
SNL’s “Weekend Update” Has Nothing on the Software Industry
Programmers, call off your drug pushers.
I know, I know… you think you’re helping. But really, you’re not. You think you’ve got my best interests at heart. You don’t. Your marketing people have convinced you that you’re “providing a service” to your customers. That you’re “ensuring quality.” Here’s where you can stick your quality, fellah.
I’m talking, of course, about automatic forced updates to my software. That’s right, I said “my software.” Not “your software,” and not “the software you created.” Once I lay my money down and get a copy of (excuse me: a license for) the software your company sold me, it’s not yours anymore. And the fundamental rules of property ownership that our society has observed for millennia make me responsible
Could the Little ESL Company be the Next Synopsys?
Back in the 1980s, chips were designed with schematics. There was a comprehensive design tool flow to support schematic-based methodology, and the world had three big EDA companies - Daisy, Mentor, and Valid - whom most folks simply referred to as “DMV”. Those three companies thrived on the tools that defined that schematic-based flow - schematic capture, gate-level simulation, timing analysis, place-and-route, and design-rule checking. Life was good, the world was stable, and folks made some decent chips.
Unfortunately, Moore’s Law kept going. Designs got bigger and schematics got unwieldy. We needed a new thing, and that new thing was language-based design.
While DMV were off trying to invent the next generation of schematic-based tools, a new company called Synopsys brought logic synthesis technology out of the lab and commercialized it. That product, Design Compiler, revolutionized chip design by raising the fundamental design abstraction level. It also shook the EDA industry at its roots. By the time the dust settled, we still had a “big 3” EDA landscape, but now the players were Synopsys, Mentor, and Cadence.
Uniquify and the Bitcoin Boom
Get out your pickaxes, canaries, and a high-powered ASIC or two - we're going mining! In this week's Fish Fry, we venture deep into the Bitcoin caves with Bob Smith (VP - Uniquify). Bob and I chat about how the Bitcoin mining race is heating up (literally) and how Uniquify is using their ASIC expertise to create super-powered machines mining today's hottest (and most controversial) virtual commodity. Also this week, I unveil a new unique Amelia-alternative to the current hardware-biased Bitcoin race. I've got two words for you: Bitcoin MMORPG. So strap on your headlamps ladies and gentlemen, we're going in.
450mm Wafers are Still Some Way Away
Years ago I saw a television wildlife programme about penguins. One image that has remained in my mind was that of the hungry penguins clustering on the edge of the ice, needing to go to catch fish, but each frightened to be the first in, as there might be an equally hungry leopard seal wanting a meal of penguin. Eventually, a penguin gets pushed in by his friends. If he survives, the rest then jump in after him.
This image has always recurred to me as chip manufacturers approach the next wafer size increase. They all want to get the benefits of a larger size wafer, but they are frightened to be the first to use the new equipment that will be needed. Eventually, someone makes the leap, and then the rest pour in.
Rolling the Dice and Spinning the Wheel
Take two steps forward and three steps back. Not all parts of our design process are created equal. In this week's Fish Fry, we examine one of the most painful, frightening, and frustrating parts of our design process - verification. My first guest is Tom Anderson (Breker Verification Systems), and we chat about formal verification, what Breker’s new verification technology TrekSoC-Si is all about, and where you can the best vinyl in Silicon Valley. Then, continuing the formal V theme - we go to Vigyan Singhal, CEO of Oski Technology. Vigyan and I dive into the details of the "Decoding Formal Club." The first rule of "Decoding Formal Club"? Well, we're gonna break that one right here. Vigyan also reveals the secret behind the name "Oski". Also this week, I investigate how Netflix is looking to read your thoughts with a little help from Amazon's Cloud services. Better put on that foil hat!
The Mistake of Marketing Market Share
We humans are a competitive bunch. Our competitive instinct inspires us to many of our greatest accomplishments. It’s not enough to simply do a thing. We need to do that thing better than the other guy, or the other team. Engineering is no different. We may pretend that we are simply “problem solvers,” but the truth is - we don’t just want to trap mice, or even trap mice efficiently. We want to design the “better” mousetrap.
After all, that is the primary purpose of modern technology - to WIN!
Of course, before we can have a proper competition, we need a way to keep score. Unfortunately, since most of us are in technology as a business, we inherit from the business world one of the world’s worst scoreboards - the market share meter.
An Anti-Engineering Concept
Synopsys recently announced the results of a flow collaboration with Fujitsu. Modestly buried in the discussion was a mention of 33% improvement in logic per area.
We’ve been at this game for a long time, and you’d think that the low-hanging fruit had long ago been picked. Which would leave us with the occasional 5-10% improvement in this and that after lots of algorithmic tweakage.
And yet here we are, in 2014, with a 33% improvement. Maybe I’m naïve, but that seems significant.
Cadence Acquires Forte High-Level Synthesis
High-level synthesis has always been the “personal jet pack” of electronic design automation. We all know that someday, “in the future,” we won’t need all these cars and roads and stuff. We’ll each have our own personal jet pack to take us quickly and directly wherever we want to go. And, when we get there, we’ll do all of our electronic designs in abstract, powerful, high-level languages and synthesize them with high-level synthesis (HLS) technology. Hunger and war will be things of the past, disease will no longer exist, and billion gate semiconductor designs will be automagically conjured up from a few simple lines of easy-to-understand algorithmic code.
Timing analysis and RTL debugging? Bah! Those will be problems of the past - like repairing broken wagon wheels. In the future, our designs will be correct-by-construction masterpieces,