Fish Fry is getting down to bare metal. We’re talking the who, what, where, and how of multi-substrate technology and checking out why the tools of today may not be up to snuff for tomorrow’s 3D IC packaging. Also this week, we look at the challenges of 100G designs and investigate why Portland, Oregon was ranked the second nerdiest city in the United States.
Xilinx Upgrades Vivado
The big battle in FPGAs has traditionally been fought at the chip level. For years, we have endured press release skirmishes over who had 20% lower power or 10% more LUTs on their devices. FPGA companies’ boom and bust years hinged largely on who got to market first with next-process-node silicon. This Moore’s Law arms race has escalated for over two decades, with staggering costs. Today, if you don’t have a 9-figure sum to invest, you’re not going to have FPGAs on the next process node.
In parallel to the silicon race, however, another war has raged - albeit less visibly. This quiet competition is more likely to determine business success over the coming years than silicon. This battle is over design tools.
Fish Fry is headed to the Land of Next this week - the next process nodes, the next big breakthrough in brain sensor technology, and the next Kickstarter investment you should consider. My guest is Wilbur Luo (Cadence) and we’re talking 16, 14, and 10nm, what’s in store for these next process nodes, and how the design challenges associated with FinFETs are going to keep us on our toes.
From Silicon to Tools and Back Again
With Moore’s Law in our back pocket, we’re hitching a ride to 2015 and the next process nodes. That's right, we’re talking hardcore chip design. From your silicon dreams to their verified reality, we're looking at each step of the chip design process with Frank Schirrmeister from Cadence Design Systems. Frank and I are going to chat about some serious top-to-bottom design flow business and try to map out a path to the future.
Tanner EDA Moves to OpenAccess, Integrates Digital More Tightly
It can be cool living on an island. As long as there are reasonable resources available, you can remain slightly detached from whatever larger landmass lies nearby and do more of what you want with less interference.
But at some point, you’re probably going to need to get to a continent. Perhaps to get stuff that’s unavailable locally; perhaps to send goods over. Regardless, that span between island and mainland can be quite the bottleneck. In fact, at times you may even find yourself wanting to replicate some resources on the island so you don’t have to go anywhere else for them.
EDA, Ethics, and Energetic Engineering
All aboard! The train is leaving the station. This week we’re taking the EE express from EDA station through some twisty turns in the mountainous region of ethics in our fair semiconductor industry, and then it's on over the hill to some awesome energetic engineering. We're checking out the EDA goodness that is CDNLive including the seriously Sci-Fi movie in one of this year's keynotes. On our next stop, we're looking into the role that ethics plays (and should play) in the semiconductor industry with Xerxes Wania (CEO - Sidense), and we're also grooving to a whole new way to do The Harlem Shake - engineering style.
Xilinx and Altera Square Off on the Future
If you have a visit with Xilinx and Altera these days and ask them about FPGA design methods above and beyond RTL, you’ll get very different answers. Xilinx will tell you they’re having great success with high-level synthesis (HLS). Altera will tell you that OpenCL is the wave of the future. Both sides make compelling arguments, which sound like they have nothing whatsoever in common. What does it all mean?
We all know that RTL design is tedious, complicated, and inefficient. We’ve known it for twenty years, in fact. To paraphrase Winston Churchill: RTL is the worst possible way to design electronics - except for all of the other ways that have been tried. (OK, and we know - Churchill was actually paraphrasing someone else. See? IP re-use works, even in politics!)
It’s Getting Hot at the Top
The FPGA market is, in many ways, a microcosm of the explosive and volatile semiconductor industry. FPGAs leapt to the front of the line in new process technologies about a decade ago - assuming the role of canaries in the Moore’s Law mines. Every time the semiconductor industry managed to reach a new technological milestone, FPGA companies raced to get the first devices to market - in order to capitalize on the bounty of the new node.
Unlike other semiconductor devices - processors, memory, etc. - FPGAs are in a unique position to take maximum advantage of Moore’s Law improvements in semiconductor technology. FPGA companies turn this technology advantage into market advantages - and into some of the biggest margins in the world of semiconductors. Each new process node brings a bounty to the world of FPGAs - usually in the form of lower power consumption, greater density (and thus greater functionality), larger IO capacity and bandwidth, and - to a lesser degree, more speed.
DVCon, Aldec Meets Hitatchi, and Parties Galore
In honor of DVCon this week, we're rounding up all the verification jokes we can muster. "I just finished verifying my multicores and boy are my ARMs tired." Or maybe: "How many verification engineers does it take to change a lightbulb?" "None, of course - but they will be able to confirm that the bulb has actually been changed." Or how about: "Seriously folks - take my dev-kit... Please!"
Cyclos Brings the Past Into the Future
Back in the old days, they really knew how to make clocks. Their energy sources were less than ideal - usually a big tensioned spring or an elevated mass on a chain. They wanted whatever energy they stored there to last as long as possible, as it was usually recharged manually by humans. Their go-to solution was simple harmonic motion - usually in the form of a pendulum. As long as they tuned the resonant frequency of the pendulum to the frequency they needed for their clock, the system would tick and tock for days - at a steady pace - using very little of the precious stored energy.
It was all about resonance.
Cadence’s Virtuoso for Advanced Nodes
Analog designers bear a heavier burden than many other designers. If you’re a digital guy, someone is out there creating cells for you, abstracting away the nasty bits so that you can operate unsullied in a land of make-believe that, magically, seems to work.
No such luck for the analog engineer. He or she has to do a lot of heavy lifting on his/her own. And this is largely of their choosing, since “trust” is not easy for analog folks: it’s too easy for someone else to make their design look bad.
Plunify Sends FPGA Tools Aloft
The Cloud… Oh, the Cloud. Always right there, the answer to all our IT problems, and yet… and yet… for designers, the promise seems to remain just out of reach as deal-breakers remain to be solved.
We’ve looked at cloud computing before, and we’ve seen new companies enter and leave the cloud. And opinions are certainly not solidly aligned behind the concept. But the discussions have largely involved EDA companies or other tools. Completely missing from the conversation have been what are probably the most universally used tools of all: FPGA tools.
EDA Tools for the 99%
It’s freezing outside, but we are determined. We’ve got our sleeping bags, our unshaven faces, and our steely determination. We are occupying FPGA and demanding better tools. Is anyone listening? We represent the 99%!
Most people in the industry would tell you that there are three big electronic design automation (EDA) companies in the world. And there’s plenty of evidence to support them. Every industry analyst for the past 20 years has tracked the same old “big-3” EDA companies doing the same old “big 3” things. If you could look into the revenues and R&D expenses for those big 3 companies, however, I’m guessing that you’d find that the big 3 are spending most of their time and energy catering to about 1% of the world’s electronic engineers.
Synopsys Nets EVE
This was no mystery match-up. People have been asking the question for a long time and only recently got their answer: When is Synopsys going to buy EVE?
For those of you not in the thick of the emulation world, EVE makes emulators – well, actually, that depends on whom you talk to – more on that shortly – but most agree on this basic point. And Synopsys was the only one of the big three EDA guys without an emulator position. And there are only three major emulation platforms in existence: Cadence’s Palladium, Mentor’s Veloce, and EVE’s ZeBu. That left EVE as the obvious electron and Synopsys with the obvious hole.
So the electron has now filled the hole.
Don’t Give Up on Simulation Yet!
It has been widely documented that the complexity of system-on-chip (SoC) designs is increasing exponentially, with most SoCs now including multi-threaded processors and many memories with multiple clock domains.
The ITRS report of 2010 shows that the number of processors for portable consumer devices is expected to increase ten-fold between 2009 and 2016, with the performance of each processor leaping 50x over the same time period. ITRS prognosticates that consumer SoC devices could embed 75 processors 10 years from now. Of course, this will be achieved under the constraint of a constant power budget. And, to top it all, design and verification schedules are shrinking. Somehow, it is not surprising a study conducted by Mentor Graphics reported that more than 70% of designs need at least two respins.