A Look Back at 2011
Yawn! Another boring year of exponential improvement in capability, cost, and power consumption. Bo-o-oring. When will something truly exciting happen in electronics? It’s just the same old grind, year after year, with nothing all that interesting going on.
Moore’s Law is a harsh mistress. It sets the bar for our industry at an incredibly high level. If you manage a 2x improvement in everything you do every two years, there’s not really anything of interest to report. You met the standard - status quo - move on along - nothing to see here. Furthermore, if you try to brag that you’ve “doubled” this or “ten-times’d” that, you get thrown into the bin of “marketing-hypers” and your credibility plummets.
Horrendous quote of the day – “27% of the industry requires 3 or more spins.” This is the headline on a slide from Harry Foster, of Mentor, based on a large worldwide survey of silicon and FPGA implementers and their verification problems, conducted by Wilson Research in 2010. OK, the positive side is that 73% get it right by second spin, and a further 23% by the fourth time round. But with spins costing multiple millions of dollars, you have to have a huge market for a chip to justify that number of spins, and a market that is prepared to wait for the chip to arrive, since, by most estimates, a re-spin is going to take three or more months. And re-spins are only part of the reason why 66% of projects are delivered late.
How EDA and Disneyland May Have More In Common Than You Think
Did you ever consider that EDA is a lot like Disneyland? I know it may sound a little kooky but check out this week’s Fish Fry to find out more! I interview Shawn McCloud (Vice President of Marketing - Calypto Design Services) about Catapult-C’s transition to Calypto, the ambiguous nature of the term ESL, and what Calypto brings to the EDA party. Also this week, I interview Shishpal Rawat (Accellera Chair) about why it's important to have IP standards and where he sees IP and system design standards headed.
How do you get from an idea to an ASIC? Classically you shell out multiple dollars for a design tool-chain, and many more dollars for people to drive it. After a lengthy period of definition, design, and verification, you send data to a foundry, pay many more millions of dollars for a mask set, and get back, weeks later, a box of wafers. Now you spend even more money on probing the wafers, and, if you are lucky/skilled, you have a working device and can move into production – that is, after putting together a logistic chain for running the devices from the foundry through a test facility and then an assembly house and finally back to where you need to use the devices. If you are not lucky/skilled, you pay even more dollars for the design to be re-worked and more millions for a new mask set, and then you still have to put together your logistics chain.
A Closer Look at Cell-Aware Modeling
Chip testing is always a delicate balance between testing enough and not testing too much. In reality, you want to find the “necessary and sufficient” set of tests for best quality at the lowest test cost. That’s a tough thing to get right.
Throw on top of that goal the fact that SoCs and other modern digital chips require automation to generate test vectors. Even if you find that perfect test balance, if you can’t figure out how to craft an algorithm to implement that balance automatically, it becomes an academic exercise.
Xilinx Premieres Premier
In the years we’ve been covering FPGAs, the technology and the market have been expanding in all dimensions. The devices themselves have grown exponentially bigger, faster, more capable, and more complex. The number and variety of applications have expanded too - with new application areas annexed into the FPGA arena on a regular basis. FPGAs have branched out from simple glue logic to complex system-on-chip integration devices in a wide gamut of markets and systems.
Combining Emulation and Offline Debugging
Today’s system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers given the challenges of controlling various components (including the microcontroller, microprocessor or DSP cores, peripherals and interfaces). Accordingly, leading semiconductor companies are working to integrate software development and validation with silicon design and verification. One obstacle to such integration is the difficulty in effectively debugging early-stage embedded software. In this article we describe a way around this obstacle by way of a new software debugging methodology for software and system-level integration.
Zuken Redesigns their Board Tools from Scratch
Anyone who’s ever done any serious remodeling of their home knows the big decision. At some point, wouldn’t it really be easier just to mow down the existing structure and start over?
Little by little, as you add new ideas – “while you guys are at it” – the costs mount, and that’s even without considering the surprises that are inevitably encountered. And if you go from a two-dimensional home – one story – and add a third dimension, it gets crazier. Most single-story homes aren’t built strong enough to support a second story. So you end up doing things like building a separate support framework to hold up the new top floor or, even more crazily, hoisting the original house up to make it the top floor and then building a new first floor under it. (Yes, people do this.)
In 1999, DAC (the Design Automation Conference) was in New Orleans. The industry was at the height of its growth, and, when you got off the plane, it looked as though at least a third of the cabs had illuminated Synopsys advertisements on their roofs. There were almost 250 exhibitors, many of them recent start-ups, and it took forever to get from the show booths to the demo booths. In the evening, DAC vendor parties were everywhere, and, despite the humidity and heat, it was a wonderful time to hear about new ideas.
Tools, IP and Processors, Oh My!
ARM TechCon was a hip and happenin' show this year and I've got the interviews to prove it. This week I interview Tony Xia and Amit Bhojraj from NXP Semiconductor about their new 49 cent 32-bit microcontroller and why they were encouraging designers to dismantle, maim and otherwise destroy their old 8- and 16-bit development boards. From the tool side of the ARM community, I also interview Thomas Sporrong from IAR Systems about the newest version of the IAR Embedded Workbench and how IAR's acquisition of Signum Systems expanded their already wide range of tool offerings.
It is strange sitting indoors on a grey wet day in Belgium -- and Belgium does pretty good grey and wet in October -- listening to people talking about photovoltaic cells. But then imec, in Leuven, Belgium, is a pretty strange place.
When Bryon wrote about imec earlier this year, he commented that, even with the steady stream of press releases, it was difficult to get a handle on what the organisation actually does.
Altera Boosts Video Analytics
The age of intelligent video is upon us. We’ve all played with the new Kinect devices from Microsoft. We’ve read about lane departure and collision avoidance systems being integrated into cars. We’ve heard about technologies like facial recognition being used in security applications. No longer are we content to stream “dumb” video from place to place. While the master control room with giant arrays of video feeds may make a compelling image for science fiction, the reality will be more like a giant array of cameras - and a very small number of monitors - showing us only the things that actually deserve our attention.
Vennsa’s Debug Technology and Fish Fry Secrets Revealed
In this week’s Fish Fry, I interview Andreas Veneris (CEO - Vennsa Technologies) and Sean Safarpour (CTO - Vennsa Technologies) about the history of debug and how exactly Vennsa fits into the big picture of design automation. I also investigate how the University of California Riverside is looking to re-invent electronic computation, and I reveal five things you may not know about Fish Fry. I also have another Amazon.com gift certificate to give out this week, but you'll have to listen to find out how you can win.
Springsoft Provides Access to More Data
At times it’s seemed a sotto-voce religious war.
One side says that a clean user interface aids productivity. The other side says that, well, quite frankly, a graphic user interface (GUI) is a toy, not meant for serious work.
One side says that command-line work is the only real way to do things; the other makes the accusation of engineers trying to keep things obscure and difficult as a form of job security.
Focused Expression Coverage Explained
When you think about it, simulating your FPGA is a lot like exercising on a treadmill. You do both of them because you want to avoid bad consequences. Some people seem to like doing it, though you might not see it that way. And you may or may not yet have seen the positive consequences in your life.
In both the case of the treadmill and of FPGA simulation, the biggest question in your mind is "When can I stop?" This is a tougher question for simulation because you don't have a sadistic trainer who makes you keep going.