Good Pieces Don’t Always Make a Good Whole
It’s seductive logic. If the pieces are good, then the whole, which is but an assemblage of known-good pieces, must be good.
I used that same logic as a kid. Orange juice is good; Cheerios are good. Ergo, using orange juice instead of milk should provide a delicious breakfast.
Wrong. That was a lesson I remember to this day. I could never quite put my finger on exactly why those two things didn’t work together – there was no obvious reason; they just didn’t.
Synopsys Attacks SEUs in FPGAs
A few years ago, one FPGA vendor, Actel, was quietly shouting in the corner. “Hey! Single event upsets (SEUs) are a big problem for FPGAs!”
The other FPGA companies replied with a thoughtful technical analysis of the situation: “Hey, Actel - SHUT UP!”
OK, maybe that’s not exactly the way it went down, but the idea is basically right. You see, Actel’s history is in super-high-reliability FPGAs for use in space. Up in space, there are lots of tiny particles flying around with a lot of energy. When one of those particles hits a vulnerable part of an IC (like a storage element of some kind), it can flip the bit from one to zero or zero to one. As your razor-sharp digital design mind might be telling you right now, this is really bad.
Calypto’s Power Optimization and the Find Amelia at Design West Contest
In this week’s Fish Fry, I dig into the multi-layered world of power optimization with Shawn McCloud (Vice President, Marketing - Calypto). Shawn and I discuss the problems surrounding power reduction in today’s smaller geometries, and why he thinks power optimization is ignored by many designers. I even grill Shawn about why he has a ban on high heels at his house. Also this week, I unveil the details of EE Journal’s first conference contest called “Find Amelia at Design West” and even throw out a couple super secret hints on how you can find me and win a MAX V CPLD Development Kit (courtesy of Altera) right there at the show.
Considering EDA Tool Longevity
There is a story in the American South about two “country boys” who walk into a lumber yard and ask to buy some wood. The lumber yard attendant asks what size they want. They look confused. He gives them some choices “two-by-fours, two-by-sixes, four-by-fours...”
They step aside for a minute to confer with each other. “We’ll take two-by-fours.”
The lumber yard attendant takes them to the aisle with the two-by-fours. “How long do you need them?”
Look out! A new way to verify is coming your way. In this week’s Fish Fry, I check out Synopsys’s new Verification IP announcement with a special in-depth interview with Neil Mullinger from Synopsys. Neil and I discuss the details of this new verification platform, what markets it's destined for, and why whipping up your own verification IP may be a thing of the past. Also this week, I look into a new development in transistor technology headed up by a team at the University of Tel Aviv and why it may or may not involve deli meat.
MathWorks Automates HDL Creation
Quick! What’s the fourth largest EDA company in the world? Most of us in the industry can rattle off the “Big 3” right? “Daisy, Mentor, Valid.” Oops, my time machine was off by about 30 years. How about “Synopsys, Mentor, Cadence”? After that, it gets a bit dicey - if we counted Magma, that would be a possibility, but we need to chalk them up to Synopsys now. For those of us who think FPGA companies are actually EDA companies with a different business model, Xilinx and Altera would be in the top four or five. Beyond that, it drops off -- a lot.
DVCon 2012 Breakdown
Welcome to the soothing waters of verification. Jump right in, the water is warm! This week's Fish Fry is all about design verification and DVCon 2012. I sift through all of the details of this year's show: the keynote, the various announcements unveiled at the show, the happy hour expo show hours and even the eerie decor of the Doubletree Hotel. In a special DVCon interview double header I chat with both Shakeel Jeeawoody (Blue Pearl Software) about getting your constraints right for HDL-based designs, and I also chat with Anupam Bakshi (CEO - Agnisys) about how Agnisys is attacking a brand new part of the EDA/verification market.
Altium's Innovations, Death Star BOM and Retro Games
In this week's Fish Fry, I look at the importance of ecosystems - in today's electronic products as well as in the tools we use as designers. I chat with Sam Sattel of Altium - one of the most progressive companies in the industry in establishing a cloud-based ecosystem for electronic design. We discuss the most recent innovations at Altium, including the new tools available in Altium Designer and the interesting way Altium deals with software updates. This week I also look into the projected BOM cost for a real-life Death Star and unveil my favorite place to play retro video games.
22nm Tri-Gate Process Should Bring Rewards
We all knew it was coming, but Tabula “officially” announced this week that they are producing their next yet-to-be-announced family of FPGAs on Intel’s 22nm Tri-Gate process. As one of the worst-kept secrets in the programmable logic industry, the Intel-Tabula relationship hardly comes as a surprise. The announcement was widely leaked about a year ago when Achronix formally announced a similar relationship with Intel.
What does it all mean?
Cadence and Samsung Do Some Pipe Cleaning
Semiconductor technology just gets curiouser and curiouser as feature sizes shrink. In real life, that means that EDA tools have to work harder and harder to figure out what’s going on and help engineers implement enormously complex designs. As usual, the problem can be boiled down to things that didn't use to matter becoming a problem
Of course, at the extremely tiny level anticipated by technologies like carbon nanotubes, things change completely. But that's still research. Leading-edge designs today are still using "conventional" processing, but making a real design work isn't easy.
(and Some Good Tools)
PCB problems got you all tangled up and blue? Never fear, all you need is love. Well, that and some good tools. This week my guest is Steve McKinney (Mentor Graphics). Steve and I are going to talk to about Mentor’s HyperLynx tool suite and why the newest features of this tool may make those pesky PCB problems a thing of the past. Also this week, check out why power and system management decisions might best be made sooner than later.
EDA is Not Quite Dead After All
When companies become zombies, it’s not quite as obvious as with humans. Sure, the symptoms are similar - being dead but walking around as if still alive, no capacity for rational thought, pursuit of a single-minded hunger - all while the inside is rapidly decomposing. Oh, and then there’s the smell.
The Moore’s Law apocalypse is taking place in the world of custom chip design right now, and by all rights EDA companies should be among the walking dead - mindlessly scouring the engineering countryside for leftover morsels of brains.
Packet Plus Brings Debugging to Networking Engineers
Networking engineers are some of the best and brightest among us. There are good reasons for this. Designing networking equipment is a demanding discipline, spanning a wide gamut of areas from analog and signal integrity to digital design to software - and integrating all of these elements at something near their maximum performance potential. In order to get a competitive piece of network hardware out the door, you are literally designing at the bleeding edge of everything.
You are designing a new product as an SoC and need some processing power - not a huge amount - and you have tight power and real estate budgets. So you drop in an 8051 core. Job done? Well, not according to the folks at Cortus. These guys, a multinational mix of people based in the Southern French town of Montpellier, whose backgrounds include working on processors for Intel, Bosch, Infineon, Siemens, and Synopsys, are likely to say that you may have made a poor move. Your real estate and power budgets can be achieved with a processor that will also give you a great deal more processing horsepower and a lower overall cost of ownership - their APS3 32-bit core.
During the Christmas break, I took time out from roasting an ox on the open fire, distributing presents to the assembled multitude of staff, chasing foxes across the rolling acres of Selwood Towers and feasting, wassailing and carousing to think about the past year and embedded technology stuff. I managed to overcome the urge and went back to roasting an ox etc, but, now the break is over, it seems worth having another think.