An Attempt at Understanding the Basics of DO-254
We recently invoked the fear of slipshod software programming as we attempted to slog through the maze of safety-critical standards facing software engineers.
But guess what: programmers aren’t the only ones capable of turning out shoddy goods. Hardware engineers can, also. But, unlike the software world, the focus in the hardware world seems to be more squarely on one standard: DO-254.
DO-254 appears to have much in common (other than origin) with DO-178. So much so, in fact, that I found a DO-254 blog site with FAQs that appeared to be copied verbatim from a set of DO-178 FAQs, with a sloppy job of search-and-replace that left such odd statements as “avionics systems are comprised of both hardware and hardware.”
How Rajeev Madhavan is Taking Magma to the Next Level
In this week's Fish Fry, Amelia interviews Rajeev Madhavan (Magma CEO) about Magma’s Silicon One initiative, how he thinks Magma fits into the EDA ecosystem and where EDA should be headed in the future. Also, Mentor Graphics plays musical product lines and Catapult C finds itself with a chair....at another company. Amelia gives some wild speculation on what actually happened.
There's another DE0-Nano Development Board to be won, but you'll have to listen to find out how to get it.
As the complexity of modern FPGAs and ASICs increases, engineers are discovering that verification using HDL simulators alone is not enough to fully test system-level design requirements in an efficient and timely manner.
Many engineers are now deploying FPGAs for algorithm acceleration and prototyping. Using FPGAs to process large test data sets enables engineers to rapidly evaluate algorithm and architecture tradeoffs and test designs under real-world scenarios without incurring the heavy time penalty associated with HDL simulators. System-level design and verification tools like MATLAB and Simulink enable engineers to realize these benefits by rapidly prototyping their algorithms on FPGAs.
An Outsider’s View of the ARM Cores
Are you in or are you out?
If you’re out, this is for you. If you’re in, it’s a review.
It’s an ARM core decoder of sorts.
You see, whenever a company like ARM or Intel generates a universe of its own, two things happen. One is that it carries a long legacy, courtesy of its long history. And, as things change, or as the roadmap undergoes strategic alterations, what might have been simple starts to become complex. The burden of acknowledging the past weighs on decisions for the future. If you weren’t an insider, if you weren’t watching all the moves and trying to understand them, you could end up lost and confused.
Bruggeman Exits Cadence and Forte Makes a Claim for High Level Synthesis
In this week's Fish Fry, Amelia interviews Sean Dart (Forte Design Systems CEO) about where he sees the future of SoC design and how high level synthesis will play a part in the years to come.
Amelia also tries to sort through the details of John Bruggeman's recent departure from Cadence Design Systems as Chief Marketing Officer and investigates how this shift will affect the future of Cadence's EDA360 manifesto.
She has a DE0-Nano Development Board to give out this week, but you'll have to tune in to find out how to win.
Verifying a DSP in an FPGA
FPGAs are an excellent choice for speeding the silicon realization of complex digital signal processing (DSP) algorithms. However, the flexibility of the fabric cannot supplant the complexity of the verification. Traditional FPGA “burn-and-churn” techniques must be replaced with a plan-driven approach that captures the overall verification intent. From there, the randomized tests constructed with Accellera’s Universal Verification Methodology (UVM™) should be combined with formal analysis to predictably converge the verification. With a suitably sophisticated approach, the DSP-FPGA marriage will be a happy one.
POCV is the Latest Salvo in Improving Timing Analysis Accuracy
When I was a teen, I remember someone coming to help my Dad plan a big move of some piece of equipment on our orchard. What struck me was how this guy could pre-visualize all the various scenarios and then consider the consequences and, in particular, all the things that could possibly go wrong for the different cases.
I was pretty impressed. It seemed like such thorough analytical capabilities were a skill and a gift. Over time, however, I’ve noticed that such an ability isn’t always appreciated. Because most of the world likes to assume best-case conditions, the “value add” of the more thorough approach is to point out that there are potential negative consequences too. Which makes you Mr. Negative. The pessimist. Always there to dash cold water on a hot idea. Doesn’t matter if you’re right.
3D gets lots of attention these days. Whether it’s the massive success of a movie that spawns a gaggle of followers making every possible consumer item 3D, the added dimension of the fin on a FinFET (or tri-gate) transistor, or the stacking of chips using TSVs or other technology, you just can’t seem to go wrong with 3D.
Finding that Happy Medium
I used to be a die-hard manual transmission driver. Even before I drove a car, I had learned how to double-clutch for smooth on-the-go gear changing on our Case tractor (which didn’t have synchronized gears because it wasn’t intended to be shifted on the go). My grandmother insisted on a manual transmission up until she stopped driving in her 80s (or later?): “I vant to do it myself!” (That’s a Swiss-German accent there…)
I finally had to rethink my principles when I got a cell phone. The moment of truth came when I was at a stoplight waiting to turn left while talking on the phone. The light turned green and I proceeded, but realized I didn’t have enough hands: I needed to turn, change gears, and hold the phone, all at the same time.
Lauro Rizzatti Talks Emulation and IBM's New Memory
In this week's Fish Fry, Amelia interviews Lauro Rizzatti (Vice President of Marketing, GM of EVE-USA) about emulation, verification, and why Lauro thought he was planting pepperoni in his garden in Italy.
Also this week, Amelia checks out the new phase change memory unveiled by IBM and investigates how this new memory technology may change the electronics industry as we know it.
Amelia has a fun new nerdy giveaway to give out this week, but you'll have to listen to find out exactly what it is!
Does a Standards-Based IP Strategy Hurt Competition?
In today’s global electronics economy and, more important, global techonomy, successful companies have to make careful decisions where they will differentiate and where they will standardize. Nowhere is this more evident and crucial than in the fabless semiconductor arena. Since fabless companies have (as the name implies) no fab, they logically do not have the ability to differentiate themselves from their competition by superior semiconductor technology.
Of course, you wouldn’t know that if you listen to FPGA companies.
OneSpin Takes on Formal Verification Metrics
“Is this it?”
“Yeah, I think so. Drop it off here.”
“Whaddaya mean, ‘I think so’? If they don’t get the money, we’re dead.”
“I know, I know. But you can’t see any addresses here. It’s all so beat up I don’t really know which house is which.”
“And you had to go without a map. Real smart.”
“There is no map, you moron! Not even Google will drive through this neighborhood. This is, like, No Man’s Land. I just want to get in, make the drop, and get out. Look, there, those guys are watching us. Givin’ me the creeps.”
The Intersection Between Sailing and Engineering and the World's First Foot USB Controller
In this week's Fish Fry, Amelia chats with Bill Neifert (Carbon Design Systems' Chief Technology Officer) about the benefits of Carbon's pre-silicon software development and architectural analysis, and how his love of sailing intersects with his passion for engineering.
Also this week, Amelia gets into the nitty gritty details of a new 3D printer specifically created to print chocolate, and she investigates how the new foot-operated digital interface unveiled by KMI might not be all that they claim it is.
Amelia has a Lattice ECP3 Versa Development Kit to give out this week, but you'll have to tune in to find out how to win.
Many of today’s integrated-circuits (ICs) are designed to operate in low-power modes to accommodate greater analog-digital integration, faster operating frequencies, and battery-powered applications. During semiconductor manufacturing test, the majority of logic is often activated concurrently to facilitate detection of many faults within a small set of patterns to reduce test time. Activating all the logic at once uses more power than these low-power devices were designed to function under, which can cause them to fail or burn out during test.
This divergence in functional power versus test power means that the test application has to allow power thresholds to be set so that overstressing devices beyond the functional design and operation is avoided.
Happy Birthday, the United States of America. How does it feel to be 235? You really have done well since you took the training wheels off and started riding your bicycle by yourself.
Many societies have what historians call “Foundation Myths” – stories that explain how a community was established. Some myths explain societies through the acts of gods, others through the actions of people, either imaginary or real people. For example, the founding myth of the City of Rome was that twins, Romulus and Remus, who were brought up by a she-wolf, founded the city that was the heart of the Roman Empire.