iROC Attacks Cosmic Attacks
We are all under attack. Don’t bother hiding the kids; there is no escape. Well, not much, anyway. A foil hat won’t be enough to protect them, and they’d be totally abused at school in a full-body foil outfit.
This constant bombardment isn’t news; it’s the familiar neutron (amongst other particles) assault that comes from space or the materials around us. And it’s just waiting to mess up the system you designed.
Aldec Harnesses Massive Server Capacity
Warning! We are going to say the “C” word in this article. If you can’t take it, just stop reading now and save yourself a lot of heartache and grief. We know a lot of you are sensitive on this topic and have deep-rooted emotional issues about it. Our advice is to seek professional counseling.
For those of you who are less delicate (we assume you’re still reading), we proudly present a system that has the potential to accelerate your design verification efforts beyond anything you could currently achieve. You know how it goes. You do your initial debugging just fine with your local copy of your favorite HDL simulator, but then you reach a point in your project where you need to crank some serious vectors through that bad boy. That’s when it gets tricky.
As is well known, the system-on-chip (SoC) verification problem grows faster than design size, so it takes more time and effort to verify a complete SoC than an individual IP block. However, the problems with SoC verification are deeper than just the increase in size.
The biggest new wrinkle introduced by today’s large multicore SoC is the greater number of shared resources, sometimes called “points of convergence” by verification engineers.
Xilinx Rebuilds Tools - From Scratch
Let’s just start by saying that this is really a big deal.
I could come up with a lot of impressive numbers and comparisons to dazzle you with the size of the project Xilinx just publicly disclosed (although it’s been one of the worst-kept secrets in the FPGA market). In fact, Xilinx offered some sound bites to us right away - like “500 man-years of engineering effort.”
But that just doesn’t even begin to capture the scope of it.
The Common Platform Alliance Goes to 14 nm and Beyond
It’s a fine marketing line: pick a strong, simple message and reinforce it without smashing it into your prospect’s face. You want to direct someone’s actions without them feeling like they’re being directed.
Most conferences have a cacophony of messages. I’ve been asked many times, “What are you seeing at [name your conference here]?” and I’m sometimes stumped for an answer because I’m seeing so many different things. Of course, most conferences are put on by organizations whose stake is simply in putting on a conference, so the messages really come from the exhibitors or presenters, and attempts by the organizer to unify a theme seem lackluster at best.
Revitalizing the Chip Startup Environment One of today’s biggest Silicon Valley gripes is the evaporation of venture capital (VC) funding for chip startups. Since the dotcom bust, consumer application-driven silicon innovation has been reduced to a relentless chase after Moore’s Law – improving power, cost and speed for incremental multimedia and wireless enhancements in a race down the consumer product generational roadmap to Inventiveness Oblivion.
With 40+ years combined founding and joining startups and working for giant chip and systems companies, the authors have seen Valley booms and “game changer” technologies come and go. Now, though, industry veterans feel Silicon Valley isn’t re-evolving, but dying.
Achronix Introduces New 22nm FPGAs
It takes a lot of guts to go head to head with an established industry leader. It takes even more guts to go up against an established duopoly - directly in their most heavily fortified markets. Fighting against one giant is tricky. You have to look carefully to find a vulnerable spot and put all your energy into exploiting that vulnerability. Fighting against two different giants is a whole 'nother ballgame. What works against one opponent may not work against the other - and giants tend to be big and heavy. You don't want to get squished between them.
IC patterning is becoming harder and harder to visualize. And I mean that quite literally. When you glaze pottery, you apply some chemical that likely looks nothing like the final outcome, trusting that, in the heat of the kiln, the necessary alchemy will render the proper final color. Even though you couldn’t see that ahead of time. Likewise, with some upcoming silicon technologies, you will no longer be able to visualize IC patterning by looking at masks.
Mask design used to be literal. You took this material called rubylith and cut out the geometries needed to implement your circuit. You took a picture of that and shrank it down into a mask. No, I’m not old enough to remember this. Barely.
In this week's Fish Fry, I look at Intel's ever-expanding reach into the world of electronic design. I interview Jarrod Siket about Netronome's collaboration with Intel and I also investigate the recent announcement that Intel and Xilinx will be funding R&D at EDA startup Oasys Design Systems. This week I also chat with Tom DeSchutter of Synopsys about what ARM's big.LITTLE is all about and how software can help with energy efficiency in mobile designs.
Good Pieces Don’t Always Make a Good Whole
It’s seductive logic. If the pieces are good, then the whole, which is but an assemblage of known-good pieces, must be good.
I used that same logic as a kid. Orange juice is good; Cheerios are good. Ergo, using orange juice instead of milk should provide a delicious breakfast.
Wrong. That was a lesson I remember to this day. I could never quite put my finger on exactly why those two things didn’t work together – there was no obvious reason; they just didn’t.
Synopsys Attacks SEUs in FPGAs
A few years ago, one FPGA vendor, Actel, was quietly shouting in the corner. “Hey! Single event upsets (SEUs) are a big problem for FPGAs!”
The other FPGA companies replied with a thoughtful technical analysis of the situation: “Hey, Actel - SHUT UP!”
OK, maybe that’s not exactly the way it went down, but the idea is basically right. You see, Actel’s history is in super-high-reliability FPGAs for use in space. Up in space, there are lots of tiny particles flying around with a lot of energy. When one of those particles hits a vulnerable part of an IC (like a storage element of some kind), it can flip the bit from one to zero or zero to one. As your razor-sharp digital design mind might be telling you right now, this is really bad.
Calypto’s Power Optimization and the Find Amelia at Design West Contest
In this week’s Fish Fry, I dig into the multi-layered world of power optimization with Shawn McCloud (Vice President, Marketing - Calypto). Shawn and I discuss the problems surrounding power reduction in today’s smaller geometries, and why he thinks power optimization is ignored by many designers. I even grill Shawn about why he has a ban on high heels at his house. Also this week, I unveil the details of EE Journal’s first conference contest called “Find Amelia at Design West” and even throw out a couple super secret hints on how you can find me and win a MAX V CPLD Development Kit (courtesy of Altera) right there at the show.
Considering EDA Tool Longevity
There is a story in the American South about two “country boys” who walk into a lumber yard and ask to buy some wood. The lumber yard attendant asks what size they want. They look confused. He gives them some choices “two-by-fours, two-by-sixes, four-by-fours...”
They step aside for a minute to confer with each other. “We’ll take two-by-fours.”
The lumber yard attendant takes them to the aisle with the two-by-fours. “How long do you need them?”
Look out! A new way to verify is coming your way. In this week’s Fish Fry, I check out Synopsys’s new Verification IP announcement with a special in-depth interview with Neil Mullinger from Synopsys. Neil and I discuss the details of this new verification platform, what markets it's destined for, and why whipping up your own verification IP may be a thing of the past. Also this week, I look into a new development in transistor technology headed up by a team at the University of Tel Aviv and why it may or may not involve deli meat.
MathWorks Automates HDL Creation
Quick! What’s the fourth largest EDA company in the world? Most of us in the industry can rattle off the “Big 3” right? “Daisy, Mentor, Valid.” Oops, my time machine was off by about 30 years. How about “Synopsys, Mentor, Cadence”? After that, it gets a bit dicey - if we counted Magma, that would be a possibility, but we need to chalk them up to Synopsys now. For those of us who think FPGA companies are actually EDA companies with a different business model, Xilinx and Altera would be in the top four or five. Beyond that, it drops off -- a lot.