Microfluidics and FPGA Verification

Tools to Make Life Better

by Amelia Dalton

This week's Fish Fry is about tools. Not just any kind of tools - tools that can make your life better, your health stronger, and your job a little easier. First up, we check out how a team of researchers from MIT hopes to stem the tide of malaria with a new prototype device that can recognize the electrical properties of infected cells. Next, we chat with Shakeel Jeeawoody from Blue Pearl Software about how their tools can simplify the debug of your next FPGA design.


Pro-Strength Tools

Do Commercial FPGA Tools Still Make Sense?

by Kevin Morris

We’ve talked a lot in these pages over the last decade about FPGA design tools. If you’ve been following along in your readers, you know that there has been a big question mark over the commercial EDA industry as far as going after the FPGA design market. The question mark is there for good reason. The two dominant FPGA companies, Xilinx and Altera, have each made huge investments in proprietary FPGA design tools. And, while they have always made a bit of a show of partnering with commercial EDA vendors, they have competed so vigorously (particularly on price) with any third-party EDA attempt to crack into the core of their design flows that most EDA companies have kept a cautious distance from the FPGA market.

It’s easy to understand a lack of enthusiasm for FPGA from the point of view of the big EDA companies. If FPGA vendors are going to provide tools that compete with yours for - nearly free, why would you invest a lot building top-notch FPGA tools? It could be very difficult to recoup your investment. And, the company you’re relying on as a partner to build and test your tools is also your biggest competitor.


Avoiding the SoC Verification Iceberg

by Thomas L. Anderson, Breker Verification Systems

It is a truth universally acknowledged, that an SoC in possession of well-verified IP, must be ready for tape-out. With due apologies to Jane Austen, this “truth” is more fantasy than fact. Of course, the IP components that make up a system-on-chip (SoC), whether from internal or external sources, must be thoroughly verified. However, this does not imply that simply plugging together well-verified IP will yield a functionally correct SoC. The “stitch and ship” approach introduces serious risks to an SoC project that can only be mitigated by a commitment to true system-level verification.

Too many SoC projects perform minimal verification on the complete chip. Verifying that each IP has been “stitched” in correctly is usually the first step. Formal analysis can be 100% effective at verifying IP and chip I/O connectivity. Unfortunately, most SoC teams do not go much further. Usually, they create a minimal testbench compliant with the Universal Verification Methodology (UVM) standard and run some basic tests –– confirming that a key IP block can read and write from memory or chip I/O pins, for example.


Software Is In Style

New C-Level SoC Verification Options

by Bryon Moyer

System-on-chip (SoC) verification is dominated by hardware verification languages and methodologies. Because you’re verifying hardware. Duh.

But, by definition, SoCs have processors that will run software. And that software represents a higher-level source of stimulation and observation for testing how well the IP blocks that make up the SoC work together.

It’s called software-driven verification, and we’ve looked at the concept before, both at the basic level and in more detail, via Breker’s solution. The former conceptually covers issues common to anyone trying to address this space, while the latter focuses more specifically on how one particular company tries to solve it.


Looping the Law

Feedback Drives Design Evolution

by Kevin Morris

Moore’s Law tells us that we should be able to double the number of transistors on a chip every couple of years. And, for about five decades, that has held mostly true. There are corollaries to Moore’s Law (that we have conveniently retrofitted as the years have passed) that say we should get some proportional increase in speed and improvement in power consumption as well. But, still considering all that, Moore’s Law is mainly about lithography - we can print things smaller and smaller on silicon, and we get lots of great benefits when we do.

Nothing in Moore’s Law says we’ll be able to do anything useful with all those transistors, however. It’s up to us, as engineers, to figure out how to take advantage of the bounty that Moore’s Law is giving us. At first, it was pretty easy. It didn’t take a lot of imagination or design savvy to get a few dozen, a few hundred, or even a few thousand transistors to work in concert doing something useful and interesting. As we got into the tens and hundreds of thousands, millions, and billions, however, engineering productivity became a serious problem - a serious problem, which, of course, gave birth to the EDA industry.


Cloudy with a Chance of EDA

FPGAs and Design Automation in the Cloud

by Amelia Dalton

Fish Fry heads into the cloud this week. We talk with two different CEOs from two different EDA companies about how their forays into the cloud set them apart from the rest of the EDA pack and promise to make our design lives a whole lot easier. With Dr. Raik Brinkmann (CEO - OneSpin Solutions) we discuss OneSpin's formal verification tool suite and how it works in the cloud, and why Raik thinks karate and engineering have a lot in common. We also chat with Harn Ng (CEO - Plunify) about how this Singapore-based EDA company is looking to revolutionize the FPGA design process.


A Tiny Pocket of Space

The Science of a Miniscule Sample

by Bryon Moyer

Verification is the science (and art) of asking the question, “What could possibly go wrong?”

If you’ve done a good job – you think – then you would expect that the answer would be, well, not very many things. If you start musing a bit harder, you might come up with some scenarios you hadn’t initially thought of. And, depressingly, the more you think about it, the more problems you can probably come up with.

It’s one thing to identify all the things that could go right or wrong in a design; it’s yet another to itemize all of the conditions leading to those good or bad outcomes, especially when it comes to a full SoC (which, mercifully, isn’t done all by you, which means there are other people you can point to if things go awry). But, in a wide-ranging discussion with Breker’s CEO Adnan Hamid, we discussed the scope of the problem – especially when taking a high-level system view.


Weighing UltraScale

Xilinx Announces New Architecture

by Kevin Morris

In the ongoing marketing battle to see who can out-confuse the competition, Xilinx has just fired an impressive salvo. Strapped safely into the cockpit of a superlative-laden press release is an announcement of what the company is calling the “UltraScale” architecture. We would say “new FPGA architecture,” but apparently it isn’t cool to make FPGAs any more. You see, Xilinx is now in the “All Programmable” device business.

Xilinx and archrival Altera have been waging a war of words lately. But, before we whip out the hypesaw and try to slog our way through the formidable layers of marketing bluster and misdirection to find what’s actually cool in this announcement (and hang in there, because there actually is some very high-quality real content buried deep in the core of this fluffball), let’s review the current state of marketing spin in the programmable logic industry:


ECO Systems

When You Need to Make That One Last Tweak

by Bryon Moyer

OK people, let’s do this. I called this meeting because we have a problem. I know, you might think that tales of what goes on here might not make it out to the golf course and into my ear, but I hear things, OK? And sometimes I don’t like what I hear.

Lately I hear that your designs have been delayed because you keep finding things to change at the last minute. That tells me you’re being sloppy. If you did your verification right up front, you shouldn’t need last-minute changes, right? Am I right?

I’ve also heard that some of you blame marketing for tossing in last-minute feature requests after you’ve completed place and route.


Up in ARMs

Processor Optimized IP and Your Next Design

by Amelia Dalton

Fish Fry is physical this week. Yep, we're flexing our SoCs and pulling on our semicodunctor spandex. We may not be running the next design marathon, but we are diving into the world of physical IP. We're talking to Dipesh Patel (ARM) about processor optimization and how ARM is packing a serious punch with their POP IP. Also this week, we're revealing why you don’t have to choose between strictly analog or digital power supplies.


Formal in the Cloud

OneSpin’s New Spin on Cloud Computing

by Bryon Moyer

The cloud is the future of everything, they say. You won’t need a computer anymore, they say. Just a phone and ubiquitous connectivity are all you need, they say (you never, ever lose your connection, do you?).

While it hasn’t completely turned our lives upside down yet, yes, the cloud has worked its way into more and more things. And we’ve seen it tip-toe into the world of EDA, although it’s not clear that it’s really sticking so far, and it has some detractors, and there are even those who went to the cloud and then left again.

So was that not such a good idea? Is the cloud for EDA going the way of push technology?


Going Local

Local Interconnect Is New. Or Not…

by Bryon Moyer

It snuck up and hit me during a Virtuoso presentation earlier this year by Cadence. It was a reference to “local interconnect.” It was the first such reference I had seen.*

For years I’ve been thinking in terms of silicon structures connected by metal through vias and contact holes. Does this mean that a completely separate set of interconnect was snaking around underneath the metal, where prying eyes (or at least my eyes) can’t see? (Don’t worry… the NSA knows it’s there…)

That wasn’t even half the insult. Here came the really humiliating part: when I started digging around, some folks from Cadence kindly (and without audibly rolling their eyes) forwarded me some older materials on local interconnect (LI). Like… from the 70s.


IGLOO2 to You Too

by Amelia Dalton

Fish Fry is headed to the land of programmable logic this week. We're talking FPGA design tools, flash-enhanced FPGAs, and ASIC designs that won't break the bank. We're getting the skinny on Microsemi's new IGLOO2 family from Paul Ekas, chatting about FPGA partitioning with Flexras CEO Hayder Mrbet, and also checking out how Triad Semiconductor can cut your mixed signal ASIC design costs down to a reasonable and career-preserving amount.


A Clean-By-Construction Deck

Sage Introduces a DRC Compiler

by Bryon Moyer

So you’ve spent many months on a chip design project that’s winding down. Layout is done, or at least you hope it’s done, and it’s time to make sure that you did it right. (Yes, I know… most designs today will involve many people doing different things, so the “you” here is intended to refer collectively to all of you.)

That means it’s time to run your design rule checks (DRCs). And as the computer hums away on your DRC deck (presumably so-called because at one time it was a deck of Hollerith cards), inspecting every nook and cranny (you hope) for violations, did you ever wonder where that deck came from?



Margaritas, SpyGlass, and the Newest in RTL Signoff

by Amelia Dalton

Fish Fry is watching you. We know all about that lunch. The one in the break room fridge. The one you thought was yours but wasn’t, and you ate it anyway. We also know that you kinda fudged that last deadline when it came close to crunch time, and let’s not even talk about those cheat codes... OK, no - we're not really watching you but we are talking about a whole other kind of spying in this week's Fish Fry. Yep, we’re talking about spying into your RTL design. My guest this week is none other than Mike Gianfagna (Atrenta) and we’re gonna ask him about RTL signoff, spyglasses, and spicy margaritas.

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