Revitalizing the Chip Startup Environment

by Peter Gasperini (Markonix) and Oasim Shami (Comira Solutions)

Revitalizing the Chip Startup Environment One of today’s biggest Silicon Valley gripes is the evaporation of venture capital (VC) funding for chip startups. Since the dotcom bust, consumer application-driven silicon innovation has been reduced to a relentless chase after Moore’s Law – improving power, cost and speed for incremental multimedia and wireless enhancements in a race down the consumer product generational roadmap to Inventiveness Oblivion.

With 40+ years combined founding and joining startups and working for giant chip and systems companies, the authors have seen Valley booms and “game changer” technologies come and go. Now, though, industry veterans feel Silicon Valley isn’t re-evolving, but dying.

 

Staring Down Giants

Achronix Introduces New 22nm FPGAs

by Kevin Morris

It takes a lot of guts to go head to head with an established industry leader. It takes even more guts to go up against an established duopoly - directly in their most heavily fortified markets. Fighting against one giant is tricky. You have to look carefully to find a vulnerable spot and put all your energy into exploiting that vulnerability. Fighting against two different giants is a whole 'nother ballgame. What works against one opponent may not work against the other - and giants tend to be big and heavy. You don't want to get squished between them.

 

The End of Seeing Is Believing

by Bryon Moyer

IC patterning is becoming harder and harder to visualize. And I mean that quite literally. When you glaze pottery, you apply some chemical that likely looks nothing like the final outcome, trusting that, in the heat of the kiln, the necessary alchemy will render the proper final color. Even though you couldn’t see that ahead of time. Likewise, with some upcoming silicon technologies, you will no longer be able to visualize IC patterning by looking at masks.

Mask design used to be literal. You took this material called rubylith and cut out the geometries needed to implement your circuit. You took a picture of that and shrank it down into a mask. No, I’m not old enough to remember this. Barely.

 

The Long ARM of Intel

by Amelia Dalton

In this week's Fish Fry, I look at Intel's ever-expanding reach into the world of electronic design. I interview Jarrod Siket about Netronome's collaboration with Intel and I also investigate the recent announcement that Intel and Xilinx will be funding R&D at EDA startup Oasys Design Systems. This week I also chat with Tom DeSchutter of Synopsys about what ARM's big.LITTLE is all about and how software can help with energy efficiency in mobile designs.

 

Breaking the System

Good Pieces Don’t Always Make a Good Whole

by Bryon Moyer

It’s seductive logic. If the pieces are good, then the whole, which is but an assemblage of known-good pieces, must be good.

I used that same logic as a kid. Orange juice is good; Cheerios are good. Ergo, using orange juice instead of milk should provide a delicious breakfast.

Wrong. That was a lesson I remember to this day. I could never quite put my finger on exactly why those two things didn’t work together – there was no obvious reason; they just didn’t.

 

Solving the Big Secret

Synopsys Attacks SEUs in FPGAs

by Kevin Morris

A few years ago, one FPGA vendor, Actel, was quietly shouting in the corner. “Hey! Single event upsets (SEUs) are a big problem for FPGAs!”

The other FPGA companies replied with a thoughtful technical analysis of the situation: “Hey, Actel - SHUT UP!”

OK, maybe that’s not exactly the way it went down, but the idea is basically right. You see, Actel’s history is in super-high-reliability FPGAs for use in space. Up in space, there are lots of tiny particles flying around with a lot of energy. When one of those particles hits a vulnerable part of an IC (like a storage element of some kind), it can flip the bit from one to zero or zero to one. As your razor-sharp digital design mind might be telling you right now, this is really bad.

 

Spring into Action

Calypto’s Power Optimization and the Find Amelia at Design West Contest

by Amelia Dalton

In this week’s Fish Fry, I dig into the multi-layered world of power optimization with Shawn McCloud (Vice President, Marketing - Calypto). Shawn and I discuss the problems surrounding power reduction in today’s smaller geometries, and why he thinks power optimization is ignored by many designers. I even grill Shawn about why he has a ban on high heels at his house. Also this week, I unveil the details of EE Journal’s first conference contest called “Find Amelia at Design West” and even throw out a couple super secret hints on how you can find me and win a MAX V CPLD Development Kit (courtesy of Altera) right there at the show.

 

Designing for the Long Haul

Considering EDA Tool Longevity

by Kevin Morris

There is a story in the American South about two “country boys” who walk into a lumber yard and ask to buy some wood. The lumber yard attendant asks what size they want. They look confused. He gives them some choices “two-by-fours, two-by-sixes, four-by-fours...”

They step aside for a minute to confer with each other. “We’ll take two-by-fours.”

The lumber yard attendant takes them to the aisle with the two-by-fours. “How long do you need them?”

 

Getting Your Verification Ducks in a Row

by Amelia Dalton

Look out! A new way to verify is coming your way. In this week’s Fish Fry, I check out Synopsys’s new Verification IP announcement with a special in-depth interview with Neil Mullinger from Synopsys. Neil and I discuss the details of this new verification platform, what markets it's destined for, and why whipping up your own verification IP may be a thing of the past. Also this week, I look into a new development in transistor technology headed up by a team at the University of Tel Aviv and why it may or may not involve deli meat.

 

MATLAB to Hardware

MathWorks Automates HDL Creation

by Kevin Morris

Quick! What’s the fourth largest EDA company in the world? Most of us in the industry can rattle off the “Big 3” right? “Daisy, Mentor, Valid.” Oops, my time machine was off by about 30 years. How about “Synopsys, Mentor, Cadence”? After that, it gets a bit dicey - if we counted Magma, that would be a possibility, but we need to chalk them up to Synopsys now. For those of us who think FPGA companies are actually EDA companies with a different business model, Xilinx and Altera would be in the top four or five. Beyond that, it drops off -- a lot.

 

V for Verification

DVCon 2012 Breakdown

by Amelia Dalton

Welcome to the soothing waters of verification. Jump right in, the water is warm! This week's Fish Fry is all about design verification and DVCon 2012. I sift through all of the details of this year's show: the keynote, the various announcements unveiled at the show, the happy hour expo show hours and even the eerie decor of the Doubletree Hotel. In a special DVCon interview double header I chat with both Shakeel Jeeawoody (Blue Pearl Software) about getting your constraints right for HDL-based designs, and I also chat with Anupam Bakshi (CEO - Agnisys) about how Agnisys is attacking a brand new part of the EDA/verification market.

 

One Ecosystem to Rule Them All

Altium's Innovations, Death Star BOM and Retro Games

by Amelia Dalton

In this week's Fish Fry, I look at the importance of ecosystems - in today's electronic products as well as in the tools we use as designers. I chat with Sam Sattel of Altium - one of the most progressive companies in the industry in establishing a cloud-based ecosystem for electronic design. We discuss the most recent innovations at Altium, including the new tools available in Altium Designer and the interesting way Altium deals with software updates. This week I also look into the projected BOM cost for a real-life Death Star and unveil my favorite place to play retro video games.

 

Tabula Taps Intel

22nm Tri-Gate Process Should Bring Rewards

by Kevin Morris

We all knew it was coming, but Tabula “officially” announced this week that they are producing their next yet-to-be-announced family of FPGAs on Intel’s 22nm Tri-Gate process. As one of the worst-kept secrets in the programmable logic industry, the Intel-Tabula relationship hardly comes as a surprise. The announcement was widely leaked about a year ago when Achronix formally announced a similar relationship with Intel.

What does it all mean?

 

Real-World Issues at 28 nm

Cadence and Samsung Do Some Pipe Cleaning

by Bryon Moyer

Semiconductor technology just gets curiouser and curiouser as feature sizes shrink. In real life, that means that EDA tools have to work harder and harder to figure out what’s going on and help engineers implement enormously complex designs. As usual, the problem can be boiled down to things that didn't use to matter becoming a problem

Of course, at the extremely tiny level anticipated by technologies like carbon nanotubes, things change completely. But that's still research. Leading-edge designs today are still using "conventional" processing, but making a real design work isn't easy.

 

All You Need Is Love

(and Some Good Tools)

by Amelia Dalton

PCB problems got you all tangled up and blue? Never fear, all you need is love. Well, that and some good tools. This week my guest is Steve McKinney (Mentor Graphics). Steve and I are going to talk to about Mentor’s HyperLynx tool suite and why the newest features of this tool may make those pesky PCB problems a thing of the past. Also this week, check out why power and system management decisions might best be made sooner than later.

subscribe to our eda newsletter


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register