RSoft Adds to Synopsys’s Light Tools
Light has always been a finicky physical phenomenon. It seems all straightforward until you get to high school and learn about how Einstein burst our naïve bubble by positing light as a jealous god that brooks no competition in the race between here and wherever.
And then there’s that shape-shifting thing it does, “Look Mom, I’ve a wave! Ooo, now look: Ta-daaaa! I’m a particle!” That has put a permanent end to the days of blithely placing maple leaves over photo-sensitive paper to create a facsimile that can be tacked to the refrigerator. Much as the centipede trips over itself if it actually tries to think about the algorithm that orders which leg moves when, nothing about light can be simple anymore now that our age of optical innocence has flickered out.
Uniquify Makes Silicon Happen
Do you dream of silicon? Do those dreams involve full-chip implementation? (Man, you are a serious nerd). This Fish Fry dives into the dreamy details of Uniquify’s ASIC design flows, custom IP, and making your silicon dreams come true.
Are Symbolic Links Evil?
This topic was going to be a blog post, but, when the dust settled, it got turned into an article (as you can see by the length). You see, what should be a simple discussion became not so much so. And there’s a tendency in some corners of our industry not to come out and deal with an issue, but to whisper things in blogs and anonymous posts here and there, raising more questions than are answered.
My desire in what follows was originally to clear up facts. I must confess that I have not come out of my research feeling like I had a complete handle on what all the facts are – and contradictory claims remain. So I invite both the companies involved and anyone else with experience or an interest in the matter to weigh in via comments.
From Space Travel to RTL Analysis and Back Again
In this week’s Fish Fry we look into Excalibur Almaz’s plans to launch people into space. We investigate how they plan to get their space tourism business off the ground, what kind of space technology they are going to employ, and what their motivations may be for launching this high-flying company. In the second half of the broadcast, I ask Shakeel Jeeawoody (Blue Pearl Software) what Blue Pearl is all about, how they are working with Synopsys within the Symplify Pro platform, and what was happening at their recent Design Automation Conference panel.
Microsoft's New Tablet Arrives on the Scene and Atrenta Rules The Roost
In this week’s Fish Fry I check out Microsoft’s new Surface tablet and investigate how this late-comer to the tablet game might have the potential to really disrupt the competition. Also this week, I talk with Mike Gianfagna (Atrenta) about the how Atrenta is helping ARM with AMBA bus configuration, assisting TSMC with IP testing, and working with Xilinx in their Vivado Tool Suite. Mike and I fit in a little chat about their jazzy reception at the DAC Conference.
The Importance of Fun Projects in Engineering
Most little kids want to grow up to be cowboys, ballerinas, astronauts, or firemen. Not you. You wanted to be an engineer, didn’t you? You wanted to make stuff.
I’m willing bet you didn’t become an engineer or a programmer by accident. You chose that career. You weren’t born into it. You probably didn’t inherit your father’s engineering practice. Your family doesn’t come from a long line of engineers that expected you to uphold the family tradition. You weren’t assigned to Job Classification 35.984.001 by an immense and bureaucratic government agency.
You’re an engineer because you like it.
Synopsys Solves Sonic Stress with Audio IP
Jack White’s manic bawl floats like frenetic frosting over a raucous clipped riff from the Parsons Triple Jet. The live recording is a mess, mixed by a near-deaf sound engineer whose thirty years at the same venue has seen his perception of sound gradually distort into a grotesque caricature of the once legendary acoustics of the house like an audio homage to Tammy Faye’s makeup artist.
Luckily, the engineers mastering the CD were on their game, and the right noises ended up in the right places - banishing the bad memory of the concert acoustics to the round of the roadies’ repeated post-concert tales. The mix was mashed into a stream of bits - encoded and enshrined - waiting for your SoC to reincarnate the Raconteurs that never were for the eager ears of your customers.
Your SoC can do audio, right?
FPGA Partitioning for the Modern Era
If you’ve worked with large designs that need to be partitioned into multiple FPGAs, you’ve probably often thought how awesome automatic partitioning would be. You just throw your big’ol design at a fancy EDA tool, push the big green “GO” button, and BAM! Your whole design is sliced up into pieces - just like in one of those martial arts movies where the ninja slices the bad guy into about seven pieces so cleanly that he doesn’t even start to fall apart right away.
Your design would be cleanly ninja-sliced into perfect partitions that fit easily into your target FPGAs with the minimal number of inter-FPGA connections. You’d have no timing problems whatsoever, and you’d barely notice that your design wasn’t running on one big super-FPGA. Absolutely no manual intervention was required.
Jasper Restructures JasperGold
I don’t have any data to prove this, but it is my conjecture that very few of the people doing marketing in high tech have any formal marketing training. I’m not even saying whether this is a good or bad thing (you could argue it either way). But the result is that certain basic lessons get learned over and over.
For example, we get it drilled through our heads repeatedly: people don’t care about features; they want the benefits that accrue from those features. We remind ourselves of this from time to time, nodding sagely, committing to a new and better round of marketing efforts.
In this week's Fish Fry, I check out the 2012 Design Automation Conference in San Francisco, California. But we're not just covering the wide range of EDA tools at the show. Oh no, we're checking out the village that is the Design Automation Conference. To add another layer of excitement, we've got not one but three C-Level interviews to throw your way, starting with the foundry guys who use EDA tools (Jack Harding, CEO - eSilicon), then on to the VHDL parser platforms that practically every EDA company uses (Michiel Ligthart, COO, Verific) and finally to the guys who break things for a living (Adnan Hamid CEO, Breker Technologies).
Part 3: A New Role for VCs
[Editor’s note: this is the third and final installment in a series of articles on ideas for revitalizing Silicon Valley. The prior installment can be found here. Your comments – in agreement or not – are welcome.]
In the first installment of the “Revitalizing the Chip Startup Environment” article series, the Lean Chip Startup (LCS) model was introduced as a new methodology for managing the operational and financial aspects of semiconductor ventures. In the classic Geoffrey Moore chip model, the venture required anywhere from $25M (best case) to $100M+ (typical) and stood a 5%-10% chance of any sort of success.
In honor of the Design Automation Conferernce coming up next week, this week's Fish Fry is all about emulation and includes a special interview with Lauro Rizzatti of EVE. Lauro and I chat about how emulation can give you more visibility into your design than an FPGA prototyping board will, how ESL plays with emulation, and why RTL simulation may not be the best plan for future process nodes.
One Clue: It’s Not Silicon
Scaling is a wonderful thing. As we’ve been able to put more and more transistors in less and less space, all we have to do is plot the magnificence of the single-chip mega-widgetry we’ll be able to create in the years to come, and the prospects get our salivary glands going.
So, flush with the promise of the upcoming grandeur of things to be, we march on with visions of digital sugarplums dancing in our heads. Until one of those annoying guys in the meeting – you know, the one who’s always trying to toss some reality into the discussion?
Part 2: The role of ESL and Verification
[Editor’s note: this is the second in a series of articles on revitalizing the chip environment in Silicon Valley. You can find the first article here.]
One of the central tenets of the Lean Chip Startup (LCS) model is frequently executed rapid hypothesis testing to ensure that a minimum viable product is developed – a product that has all the necessary features and capabilities (and nothing superfluous) to meet the requirements of 80% of the mainstream customer base.
“Aptiv” Line of Processors: the Start of a New Generation
Blame BMW. Or maybe Sears, Roebuck & Co. The trend of classifying all your products into clearly defined low, middle, and high ranges has now extended its grasp to MIPS Technologies.
Carmakers figured out a long time ago that it would help sell cars if consumers could keep all the confusing model numbers straight. Thus, General Motors had its Chevrolet brand (low end), its Buicks (midrange), and its Cadillacs (high end). That branding strategy served the company quite well, even when all three cars were actually the same vehicle with different hood ornaments.