Unhinged with Brian Fuller
Who said electronic engineering can't be funny? (Someone who has never read this publication!) In this week's Fish Fry, we check out a brand new online television show that that aims to bring the saucy style of late night television talk shows to our engineering community. My guest is Brian Fuller of Cadence Design Systems, and we chat about why Cadence decided to make a humorous engineering-based talk show and how they are going about the business of making EE fun.
Unraveling SADP – Part 1
What follows is something I enter into with great trepidation. Getting this… article thing… to a point where you can read it has involved more brain cell abuse than I inflicted upon myself during my entire college career. OK, it sort of feels like that, anyway.
We’re going to talk about double-patterning. Yeah, I know, we’ve talked about it before and it wasn’t so bad, was it? Ah, that’s because there isn’t just one double-patterning: there are two. Actually, there are more than two, but most of the other major variants don’t seem to be finding their way into production, so we’re going to ignore them. Denial being an awesome tool when used the right way.
The Designer's Perspective
Circuit reliability verification has become a crucial step in IC design. Reliability requirements are not only growing in all market segments, including automotive/transportation, medical, mobile/wireless, and consumer electronics, but the complexity of today’s circuits is presenting unprecedented verification challenges. To get these designs to market in a timely manner, while ensuring they will perform as designed, designers need automated circuit reliability solutions that can quickly and accurately analyze these complex designs. From the designer’s perspective, two critical factors in efficient reliability verification are: • the ability to understand the logic of the circuit • the ability to recognize specific circuit topologies (patterns) associated with circuit reliability
ARM, Fujitsu, and UMC Add Their Voices
We noted recently the slight hesitation taking place in the rush to FinFETs. Some folks are taking another look at FD-SOI as a way of extending planar technology in a more cost-effective manner than what FinFETs promise.
But there’s more to planar than just FD-SOI. Some time back we also surveyed a new approach to planar transistors being pioneered by newcomer SuVolta. At the time, our focus was on how the basic transistor was supposed to work and any proof points that existed then, which were few.
Findin' Them Buggers Fast
Maybe it's an itch that just won't go away. Maybe it's a daydream buster - Aw dang, I didn't think of that. Or, maybe it's a recurring nightmare that runs you ragged each and every night. Yep, we're talking about hardware-assisted verification. It ain't easy and nobody ever said it was going to be. In this week's Fish Fry my guest is Frank Schirrmeister from Cadence Design Systems. We chat about why hardware-assisted verification is on everybody’s mind these days, and what we can do to make our verification lives a whole bunch easier.
Which is Where Your Users Are
Sometime during the last twelve months at one of the typical industry conferences, I took a typical briefing. To us in the journalism world, a “briefing” is when a company sits down with an editor like me and tells a story. Their hope is that we will retell that story. Because if the story comes from their pen, it sounds like marketing; if it comes from our pen, it sounds like journalism, which gives it an extra air of legitimacy.
Of course, if you’re like me or my EE Journal colleagues, you probably take their story, invert it, fold it ten ways, look at that one pointy bit, and focus on that. It all comes out very different from the original (but hopefully the facts are correct).
Synopsys Announces a Sensor Subsystem
There’s a scramble afoot as sensor and silicon and software and system folks try to jockey over the best way to implement and integrate sensors into a broad range of devices. You’ve got:
- Folks making sensors
- Folks making micro-controllers that can run sensor-related software
- Folks integrating sensors and micro-controllers together
- Folks integrating multiple sensors together in a single package, possibly with a micro-controller as well
- System guys controlling sensors via the AP in an SoC
- System guys including a sensor hub of some sort in an SoC
With summer drawing to a close, what better time to journey to the land of EDA - where the C is synthesized, the constraints are random, and the living is easy. We talk with Brett Cline (Forte Design Systems) about what's hot in C Synthesis these days, and we also check in with Steve Kinney from Nimbic. Not sure what Nimbic does? You're in luck - we're gonna tell you.
Zuken Expands Scope and Reach
Most of us have heard of Zuken. They have always been one of the quiet companies who made PCB layout software - and who was not Mentor or Cadence. If we decided to upgrade our board design capabilities, they were on the list of suppliers we'd consider. Nothing about Zuken particularly grabbed our attention other than the assumption that they could help us bring some order to blank FR4 just as well as the next guy.
In Japan, however, Zuken was certainly not just one of the pack. In Japan, Zuken has had dominant market share for years. If you designed boards in Japan and used anything else, you just might be eyed with some suspicion. Zuken was founded in 1976 and has over a thousand employees worldwide, so they're hardly a new kid on the block, and they are a substantial EDA company by any measure. Being headquartered in Japan, however (and listed on the Tokyo Stock Exchange), they don't show up on radar quite the same way as most of the rest of the EDA industry.
Oski Discusses End-to-End Block Verification
Formal verification has had a rough go over the years. It came onto the scene with tons of promise, and that promise remains, to some extent, promise. It’s hard to argue against the possibility of taking a spec and a circuit, pushing a button, and watching while some tool provides proof that the circuit is correct.
And watching… and watching… and, well, yeah, that’s where the problems cropped up. Waiting for an answer to some of these problems, if not done carefully, can require suspended animation so that you can be reawakened in some future year or century when the calculation is complete.
The State of the Prototyping Game
As FPGAs have gotten larger and larger, the target audience for the biggest, baddest devices has grown smaller and smaller. These days, the audience has pretty much dwindled to a single group - those using FPGAs to prototype even larger systems. Engineering teams designing the biggest, most complicated SoCs need as many gates worth of prototyping as they can get - and the people developing software for those systems need to start well before the actual hardware is working.
The FPGAs for this type of work come almost exclusively from Xilinx and Altera. On the Xilinx side, the flagship is the gargantuan Virtex-7 2000T, a 6.8 billion (yep, with a B) transistor device with two million 4-input LUT equivalent cells. The device achieves its size by 2.5D interposer-based packaging (it’s actually 4 FPGA chips interconnected on a silicon interposer) using what Xilinx calls “Stacked Silicon Interconnect (SSI)” Technology. Altera’s biggest current prototyping-targeted device is the Stratix V E - which packs a respectable 1M equivalent 4-input LUTs on a monolithic device. Not content to have the second-biggest chip in town, however, Altera has already announced a 4-million cell device in their upcoming Intel-fabbed 14nm FinFET-based device.
Tools to Make Life Better
This week's Fish Fry is about tools. Not just any kind of tools - tools that can make your life better, your health stronger, and your job a little easier. First up, we check out how a team of researchers from MIT hopes to stem the tide of malaria with a new prototype device that can recognize the electrical properties of infected cells. Next, we chat with Shakeel Jeeawoody from Blue Pearl Software about how their tools can simplify the debug of your next FPGA design.
Do Commercial FPGA Tools Still Make Sense?
We’ve talked a lot in these pages over the last decade about FPGA design tools. If you’ve been following along in your readers, you know that there has been a big question mark over the commercial EDA industry as far as going after the FPGA design market. The question mark is there for good reason. The two dominant FPGA companies, Xilinx and Altera, have each made huge investments in proprietary FPGA design tools. And, while they have always made a bit of a show of partnering with commercial EDA vendors, they have competed so vigorously (particularly on price) with any third-party EDA attempt to crack into the core of their design flows that most EDA companies have kept a cautious distance from the FPGA market.
It’s easy to understand a lack of enthusiasm for FPGA from the point of view of the big EDA companies. If FPGA vendors are going to provide tools that compete with yours for - nearly free, why would you invest a lot building top-notch FPGA tools? It could be very difficult to recoup your investment. And, the company you’re relying on as a partner to build and test your tools is also your biggest competitor.
It is a truth universally acknowledged, that an SoC in possession of well-verified IP, must be ready for tape-out. With due apologies to Jane Austen, this “truth” is more fantasy than fact. Of course, the IP components that make up a system-on-chip (SoC), whether from internal or external sources, must be thoroughly verified. However, this does not imply that simply plugging together well-verified IP will yield a functionally correct SoC. The “stitch and ship” approach introduces serious risks to an SoC project that can only be mitigated by a commitment to true system-level verification.
Too many SoC projects perform minimal verification on the complete chip. Verifying that each IP has been “stitched” in correctly is usually the first step. Formal analysis can be 100% effective at verifying IP and chip I/O connectivity. Unfortunately, most SoC teams do not go much further. Usually, they create a minimal testbench compliant with the Universal Verification Methodology (UVM) standard and run some basic tests –– confirming that a key IP block can read and write from memory or chip I/O pins, for example.
New C-Level SoC Verification Options
System-on-chip (SoC) verification is dominated by hardware verification languages and methodologies. Because you’re verifying hardware. Duh.
But, by definition, SoCs have processors that will run software. And that software represents a higher-level source of stimulation and observation for testing how well the IP blocks that make up the SoC work together.
It’s called software-driven verification, and we’ve looked at the concept before, both at the basic level and in more detail, via Breker’s solution. The former conceptually covers issues common to anyone trying to address this space, while the latter focuses more specifically on how one particular company tries to solve it.