I Spy RTL

Margaritas, SpyGlass, and the Newest in RTL Signoff

by Amelia Dalton

Fish Fry is watching you. We know all about that lunch. The one in the break room fridge. The one you thought was yours but wasn’t, and you ate it anyway. We also know that you kinda fudged that last deadline when it came close to crunch time, and let’s not even talk about those cheat codes... OK, no - we're not really watching you but we are talking about a whole other kind of spying in this week's Fish Fry. Yep, we’re talking about spying into your RTL design. My guest this week is none other than Mike Gianfagna (Atrenta) and we’re gonna ask him about RTL signoff, spyglasses, and spicy margaritas.

 

Powering Down the First Derivative

Teklatech Softens Pulses

by Bryon Moyer

When we first start learning math (or, for those across the pond, “maths” – however many of them there are), we learn about amounts. Simple numbers that describe how much of something there is at a given time. But when we grow up, we start to think about how fast those numbers change, and we enter the bewildering world of calculus and the first derivative. (Through the unfortunate mechanism of epsilons and deltas, which immediately confounds all but the most analytical folks and gives the whole thing a bad name… but I digress.)

A few years ago we took a look at Teklatech’s Power Shaping technology. Originally associated with their floorplanning focus, it evolved to be their primary purpose: to reduce the amplitude of noise on the power rail. They say that such “rail-aware” analysis is now a standard thing. So we’re done, right?

 

Let's Get This DAC Party Started

Bits and Pieces from the 2013 Design Automation Conference

by Amelia Dalton

Maybe it was the heat, maybe was the sheer number of processor guys strolling in from the greater Austin area, or maybe it was the BBQ. I’m not exactly sure what it was, but this year’s Design Automation Conference and Expo was livelier and more energetic than we’ve seen in years, and Fish Fry is taking you straight to center of the serious (and not so serious) design automation action. First, we talk about DAC with Tom Anderson (Breker) and ask him about SoC verification and more importantly, what set the Breker booth apart from the rest of the pack on the expo floor this year. Next, we chat with Anupam Bakshi, CEO of Agnisys about cavemen, automatic code generation, and booth babes…or, uh, I mean, temporary technical representatives.

 

#50DAC

Technology History Trending in Austin

by Kevin Morris

The 50th annual Design Automation Conference (DAC) in Austin Texas is a landmark event. It is remarkable to think that engineers have been using computer-aided design for electronic systems for more than half a century now. In honor of DAC’s 50th anniversary, there is a small museum in the front of the show with memorabilia (pronounced “swag”) spanning the five-decade history of the conference. Among the T-shirts, coffee mugs, backpacks, and other era-appropriate giveaways, there are photo scrapbooks of years past and samples of conference proceedings. There is even a copy of the proceedings from the very first DAC - “1964 ACM/IEE Design Automation Conference” - held in Atlantic City, NJ June 24-26 1964.

 

EDA for Sensor Fusion

Movea’s SmartFusion Studio

by Bryon Moyer

When you’re building something that’s never been built before, you’ve got a lot more work in store for you than you would if you merely satisfied yourself with what’s already been done. There are lots of unknowns, and you’ve got to explore and solve them before you can proceed.

If you’re doing an everyday human-sized project in your workshop to build something using unusual materials, you have to figure out what adhesives or other fasteners will work, whether any of the materials might interact (aluminum touching iron?), whether paints will cover adequately… You might have to try different variants or different formulations until you get something that performs well.

 

Timing is Everything

The Trouble with Timing Closure in FPGA Design

by Kevin Morris

Timing closure is the not-so-fine-print of FPGA design.

PowerPoint presentations paint the process as almost trouble free. FPGA design is simple, right? You just code up some HDL, drop it into the vendor-supplied tool suite, press the magic button - and zzzzzip! Your dev board will spring to life - blinking LEDs and detecting button presses with glee and aplomb. You even try it with the supplied sample code. Yep, sure enough. It’s like microwaving a burrito. Pop off the wrapper, run it through the process, and it’s ready to eat.

Emboldened, you embark on your first “real” design work. This takes some time, of course. You select from a nice assortment of pre-designed IP blocks, stitch them together with the vendor-supplied whizzy-GUI tool, and things are lookin’ good. You run that portion of your design through the tools and - still on track - except for a couple of things you hooked up wrong between blocks, the miracle of field-programmable custom logic is your apple.

 

Will Electrical and Mechanical Domains Merge?

A Conversation About Mentor’s FloTHERM XT Raises the Question

by Bryon Moyer

Electronics power density is approaching that of a nuclear reactor core. But don’t worry – it’s still an order of magnitude less than that of a rocket nozzle.

This was the eye-opening “got your attention?” snippet in a presentation launching Mentor’s new FloTHERM XT tool.

The idea of this particular tool is to make life easier for PCB and system designers as they manage heat by bringing together EDA and MDA (Mechanical Design Automation) data early in the conceptual stage of a design to allow earlier, faster thermal simulation.

 

The Rise of MathWorks, the Fall of EDA

Two Routes Into FPGA Tools

by Kevin Morris

Since Einstein, we’ve come to realize that more and more things depend on relativity. This is true not just in physics, but also in more human arenas like marketing and sales. Our perception of something like - FPGA tool prices, for example - might depend on whether we’re coming from an EDA background - which says that high-quality design tools cost tens- to hundreds-of-thousands of dollars for a license, or from a mass-market software background - which says that software goes for tens to hundreds of dollars a pop.

Both of these are valid perspectives. EDA companies have to charge what they do to fund the enormous engineering effort required to develop highly-sophisticated tools for a relatively small audience. Developing a good EDA tool is a much more complex undertaking than, say, the latest version of Angry Birds, and the cost of that complexity is amortized over an audience thousands of times smaller. The result - one piece of software might cost $5 and one might cost $500,000.

 

FPGA Tools, Marketing Malarkey Goggles, and More

by Amelia Dalton

FPGA Tools - can't live with them, can't design without them. This week's Fish Fry is about ending the first part of that meme and how Xilinx is hoping to make our design tool experience a whole bunch easier. My guest is Tim Vanevenhoven (Senior Marketing Manager - Xilinx) and we're going to chat about design abstraction, IP integration, and how the FPGA tool community is working together to provide more powerful, easier to use solutions. Also this week, I give a sneak preview of my previously top-secret, special-purpose augmented reality glasses - and I'll tell you how I plan to use them to cut through the marketing fog at the upcoming Design West show. Hmmm... Maybe I should do a Kickstarter project to get these guys into volume production...

 

Grenoble News

An EDA DATE in the French Alps

by Dick Selwood

DATE used to be a smaller version of DAC: a significant trade show with a small conference. Companies took large stands to show off the latest and greatest in EDA, and it was often used to pre-announce news for DAC. It alternated between Paris and Munich, both destination cities.

Today DATE is very different. It has become a deeply technical and mainly academic research-based conference, with a small show attached. It alternates between Dresden in Germany and Grenoble in France. Why, you might ask, Grenoble? It is not the easiest of places to get to, surrounded as it is by mountains. Its own, small, airport is 25 miles away. But when you start to look at what is happening there, suddenly having a technology conference makes sense.

 

My Substrate or Yours?

by Amelia Dalton

Fish Fry is getting down to bare metal. We’re talking the who, what, where, and how of multi-substrate technology and checking out why the tools of today may not be up to snuff for tomorrow’s 3D IC packaging. Also this week, we look at the challenges of 100G designs and investigate why Portland, Oregon was ranked the second nerdiest city in the United States.

 

The Bell for Round Two

Xilinx Upgrades Vivado

by Kevin Morris

The big battle in FPGAs has traditionally been fought at the chip level. For years, we have endured press release skirmishes over who had 20% lower power or 10% more LUTs on their devices. FPGA companies’ boom and bust years hinged largely on who got to market first with next-process-node silicon. This Moore’s Law arms race has escalated for over two decades, with staggering costs. Today, if you don’t have a 9-figure sum to invest, you’re not going to have FPGAs on the next process node.

In parallel to the silicon race, however, another war has raged - albeit less visibly. This quiet competition is more likely to determine business success over the coming years than silicon. This battle is over design tools.

 

Sensors on the Brain and FinFETs in the Game

by Amelia Dalton

Fish Fry is headed to the Land of Next this week - the next process nodes, the next big breakthrough in brain sensor technology, and the next Kickstarter investment you should consider. My guest is Wilbur Luo (Cadence) and we’re talking 16, 14, and 10nm, what’s in store for these next process nodes, and how the design challenges associated with FinFETs are going to keep us on our toes.

 

These Silicon Times - They Are a Changin'

From Silicon to Tools and Back Again

by Amelia Dalton

With Moore’s Law in our back pocket, we’re hitching a ride to 2015 and the next process nodes. That's right, we’re talking hardcore chip design. From your silicon dreams to their verified reality, we're looking at each step of the chip design process with Frank Schirrmeister from Cadence Design Systems. Frank and I are going to chat about some serious top-to-bottom design flow business and try to map out a path to the future.

 

Island Life Made Easier

Tanner EDA Moves to OpenAccess, Integrates Digital More Tightly

by Bryon Moyer

It can be cool living on an island. As long as there are reasonable resources available, you can remain slightly detached from whatever larger landmass lies nearby and do more of what you want with less interference.

But at some point, you’re probably going to need to get to a continent. Perhaps to get stuff that’s unavailable locally; perhaps to send goods over. Regardless, that span between island and mainland can be quite the bottleneck. In fact, at times you may even find yourself wanting to replicate some resources on the island so you don’t have to go anywhere else for them.

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