Flexras Makes a Finer Cut

FPGA Partitioning for the Modern Era

by Kevin Morris

If you’ve worked with large designs that need to be partitioned into multiple FPGAs, you’ve probably often thought how awesome automatic partitioning would be. You just throw your big’ol design at a fancy EDA tool, push the big green “GO” button, and BAM! Your whole design is sliced up into pieces - just like in one of those martial arts movies where the ninja slices the bad guy into about seven pieces so cleanly that he doesn’t even start to fall apart right away.

Your design would be cleanly ninja-sliced into perfect partitions that fit easily into your target FPGAs with the minimal number of inter-FPGA connections. You’d have no timing problems whatsoever, and you’d barely notice that your design wasn’t running on one big super-FPGA. Absolutely no manual intervention was required.

 

Formal Solutions from Formal Technology

Jasper Restructures JasperGold

by Bryon Moyer

I don’t have any data to prove this, but it is my conjecture that very few of the people doing marketing in high tech have any formal marketing training. I’m not even saying whether this is a good or bad thing (you could argue it either way). But the result is that certain basic lessons get learned over and over.

For example, we get it drilled through our heads repeatedly: people don’t care about features; they want the benefits that accrue from those features. We remind ourselves of this from time to time, nodding sagely, committing to a new and better round of marketing efforts.

 

Not Your Mama's DAC

by Amelia Dalton

In this week's Fish Fry, I check out the 2012 Design Automation Conference in San Francisco, California. But we're not just covering the wide range of EDA tools at the show. Oh no, we're checking out the village that is the Design Automation Conference. To add another layer of excitement, we've got not one but three C-Level interviews to throw your way, starting with the foundry guys who use EDA tools (Jack Harding, CEO - eSilicon), then on to the VHDL parser platforms that practically every EDA company uses (Michiel Ligthart, COO, Verific) and finally to the guys who break things for a living (Adnan Hamid CEO, Breker Technologies).

 

Revitalizing the Chip Startup Environment

Part 3: A New Role for VCs

by Peter Gasperini (Markonix)

[Editor’s note: this is the third and final installment in a series of articles on ideas for revitalizing Silicon Valley. The prior installment can be found here. Your comments – in agreement or not – are welcome.]

In the first installment of the “Revitalizing the Chip Startup Environment” article series, the Lean Chip Startup (LCS) model was introduced as a new methodology for managing the operational and financial aspects of semiconductor ventures. In the classic Geoffrey Moore chip model, the venture required anywhere from $25M (best case) to $100M+ (typical) and stood a 5%-10% chance of any sort of success.

 

Cracking the Mystery of Emulation

by Amelia Dalton

In honor of the Design Automation Conferernce coming up next week, this week's Fish Fry is all about emulation and includes a special interview with Lauro Rizzatti of EVE. Lauro and I chat about how emulation can give you more visibility into your design than an FPGA prototyping board will, how ESL plays with emulation, and why RTL simulation may not be the best plan for future process nodes.

 

The New Silicon Productivity Gap

One Clue: It’s Not Silicon

by Bryon Moyer

Scaling is a wonderful thing. As we’ve been able to put more and more transistors in less and less space, all we have to do is plot the magnificence of the single-chip mega-widgetry we’ll be able to create in the years to come, and the prospects get our salivary glands going.

So, flush with the promise of the upcoming grandeur of things to be, we march on with visions of digital sugarplums dancing in our heads. Until one of those annoying guys in the meeting – you know, the one who’s always trying to toss some reality into the discussion?

 

Revitalizing the Chip Startup Environment

Part 2: The role of ESL and Verification

by Peter Gasperini (Markonix) and Qasim Shami (Comira Solutions)

[Editor’s note: this is the second in a series of articles on revitalizing the chip environment in Silicon Valley. You can find the first article here.]

One of the central tenets of the Lean Chip Startup (LCS) model is frequently executed rapid hypothesis testing to ensure that a minimum viable product is developed – a product that has all the necessary features and capabilities (and nothing superfluous) to meet the requirements of 80% of the mainstream customer base.

 

MIPS Plants a New Family Tree

“Aptiv” Line of Processors: the Start of a New Generation

by Jim Turley

Blame BMW. Or maybe Sears, Roebuck & Co. The trend of classifying all your products into clearly defined low, middle, and high ranges has now extended its grasp to MIPS Technologies.

Carmakers figured out a long time ago that it would help sell cars if consumers could keep all the confusing model numbers straight. Thus, General Motors had its Chevrolet brand (low end), its Buicks (midrange), and its Cadillacs (high end). That branding strategy served the company quite well, even when all three cars were actually the same vehicle with different hood ornaments.

 

The Process of Process Tracking

Satin Attempts to Corral a Recalcitrant Beast

by Bryon Moyer

Want to scare an engineer? There’s an easy weapon out there. And it consists of only one word.

“Process.”

Process is supposed to mean that a company has a formula, that they have a way of doing things that works, and that it’s repeatable, and – most importantly – that it’s a feature of the company, not some individual that works there. That means the process survives even when key people are no longer working there.

 

Springtime in the SoC

Audio IP, Static Analysis and Board Member Switch-a-roo

by Amelia Dalton

In honor of the Design Automation Conference that is less than a month away, I take a little foray into the mysterious land of tools. First up, I chat with Henk Hamoen (Synopsys) about how Synopsys is working its way into audio IP, and then it's an interview with Mark Zarins of GrammaTech about static code analysis and why your level of comfort in dealing with abstraction is important to them. Finally, I have a special “News You May Have Missed" segment about some recent rumblings on the Mentor Graphics Board of Directors.

 

An EDA Foil Hat

iROC Attacks Cosmic Attacks

by Bryon Moyer

We are all under attack. Don’t bother hiding the kids; there is no escape. Well, not much, anyway. A foil hat won’t be enough to protect them, and they’d be totally abused at school in a full-body foil outfit.

This constant bombardment isn’t news; it’s the familiar neutron (amongst other particles) assault that comes from space or the materials around us. And it’s just waiting to mess up the system you designed.

 

Power When You Need It

Aldec Harnesses Massive Server Capacity

by Kevin Morris

Warning! We are going to say the “C” word in this article. If you can’t take it, just stop reading now and save yourself a lot of heartache and grief. We know a lot of you are sensitive on this topic and have deep-rooted emotional issues about it. Our advice is to seek professional counseling.

For those of you who are less delicate (we assume you’re still reading), we proudly present a system that has the potential to accelerate your design verification efforts beyond anything you could currently achieve. You know how it goes. You do your initial debugging just fine with your local copy of your favorite HDL simulator, but then you reach a point in your project where you need to crank some serious vectors through that bad boy. That’s when it gets tricky.

 

Verifying Today’s SoCs Requires a New Approach

by Thomas L. Anderson (Breker)

As is well known, the system-on-chip (SoC) verification problem grows faster than design size, so it takes more time and effort to verify a complete SoC than an individual IP block. However, the problems with SoC verification are deeper than just the increase in size.

The biggest new wrinkle introduced by today’s large multicore SoC is the greater number of shared resources, sometimes called “points of convergence” by verification engineers.

 

Kind Of A Big Deal

Xilinx Rebuilds Tools - From Scratch

by Kevin Morris

Let’s just start by saying that this is really a big deal.

I could come up with a lot of impressive numbers and comparisons to dazzle you with the size of the project Xilinx just publicly disclosed (although it’s been one of the worst-kept secrets in the FPGA market). In fact, Xilinx offered some sound bites to us right away - like “500 man-years of engineering effort.”

But that just doesn’t even begin to capture the scope of it.

 

I Can Has Roadmap?

The Common Platform Alliance Goes to 14 nm and Beyond

by Bryon Moyer

It’s a fine marketing line: pick a strong, simple message and reinforce it without smashing it into your prospect’s face. You want to direct someone’s actions without them feeling like they’re being directed.

Most conferences have a cacophony of messages. I’ve been asked many times, “What are you seeing at [name your conference here]?” and I’m sometimes stumped for an answer because I’m seeing so many different things. Of course, most conferences are put on by organizations whose stake is simply in putting on a conference, so the messages really come from the exhibitors or presenters, and attempts by the organizer to unify a theme seem lackluster at best.

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