The Mistake of Marketing Market Share
We humans are a competitive bunch. Our competitive instinct inspires us to many of our greatest accomplishments. It’s not enough to simply do a thing. We need to do that thing better than the other guy, or the other team. Engineering is no different. We may pretend that we are simply “problem solvers,” but the truth is - we don’t just want to trap mice, or even trap mice efficiently. We want to design the “better” mousetrap.
After all, that is the primary purpose of modern technology - to WIN!
Of course, before we can have a proper competition, we need a way to keep score. Unfortunately, since most of us are in technology as a business, we inherit from the business world one of the world’s worst scoreboards - the market share meter.
An Anti-Engineering Concept
Synopsys recently announced the results of a flow collaboration with Fujitsu. Modestly buried in the discussion was a mention of 33% improvement in logic per area.
We’ve been at this game for a long time, and you’d think that the low-hanging fruit had long ago been picked. Which would leave us with the occasional 5-10% improvement in this and that after lots of algorithmic tweakage.
And yet here we are, in 2014, with a 33% improvement. Maybe I’m naïve, but that seems significant.
Cadence Acquires Forte High-Level Synthesis
High-level synthesis has always been the “personal jet pack” of electronic design automation. We all know that someday, “in the future,” we won’t need all these cars and roads and stuff. We’ll each have our own personal jet pack to take us quickly and directly wherever we want to go. And, when we get there, we’ll do all of our electronic designs in abstract, powerful, high-level languages and synthesize them with high-level synthesis (HLS) technology. Hunger and war will be things of the past, disease will no longer exist, and billion gate semiconductor designs will be automagically conjured up from a few simple lines of easy-to-understand algorithmic code.
Timing analysis and RTL debugging? Bah! Those will be problems of the past - like repairing broken wagon wheels. In the future, our designs will be correct-by-construction masterpieces,
Cadence Acquires Forte
Here at Fish Fry, when big news breaks, we swim to it. When the EE landscape changes, we evolve, lose our gills, begin breathing air, and start walking on land. This is one of those weeks. When we got wind that Cadence was in the process of acquiring Forte, we jumped on the chance to get the goods on this groundbreaking news story. My guest this week is Craig Cochran (Vice President, Corporate Marketing at Cadence Design Systems) and we discuss the growing adoption of high level synthesis and how Forte plays into the Cadence system-level design flow. Also this week, we check out how the Hybrid Memory Cube aims to take out DDR, and how FPGAs can help you with your HMC heavy lifting.
Fish Fry Takes on DesignCon 2014
The lights: Fluorescent. The carpet: Padded. The lanes: Routed. Where in the world could Fish Fry be? DesignCon 2014, of course. In this special DesignCon episode of Fish Fry, we launch ourselves into the multi-faceted world of electronic design with a couple of interesting interviews. My first guest is none other than Kilopass CEO Charlie Cheng. Charlie and I get down to the nuts and bolts of non-volatile memory, and Charlie gives me his take on where he thinks the technology is headed over the next few years. Next, I chat with Mark Toth (CadSoft) about CadSoft's ubiquitous EAGLE PCB Design Software, and I get the inside scoop on the results of their recent PCB design survey.
FPGA Design Starts with You
In the early days of FPGAs, we did our work with schematics. FPGAs were small, and you could stitch together a little gate-level schematic pretty easily. Then, it was just a matter of running the FPGA tool flow, and a few seconds later you had a bitstream ready to program your cute little programmable logic device. It was all pretty easy, and - with schematics being the universal language of EE, there wasn’t a lot of special skill required.
About fifteen years ago, FPGAs outgrew gate-level schematic entry. We moved on to hardware description languages like VHDL and Verilog and began fighting with logic synthesis tools to try to get our designs to behave. This actually narrowed the field of FPGA designers somewhat. The universe of “people who knew HDL and synthesis” was quite a bit smaller than “people who could draw a decent schematic.” The FPGA companies didn’t care. They were chasing the lucrative communications and networking infrastructure market, and the folks writing the big checks had plenty of HDL experts.
A New Step, Championed by Atrenta
The concept, “High risk, high reward” doesn’t hold with semiconductors. Heck, we have an entire industry built on the notion of risk reduction: EDA. EDA tools are enormously expensive to develop and are therefore expensive to acquire by the user.
There’s only one reason someone would spend that much money on tools: because it’s going to prevent even more gargantuan losses if something goes wrong with the chip.
OK, granted, much of what EDA is about is productivity – just try cutting a few billion transistors out of rubylith and see what that does for your carpal tunnels. So, really, it’s the 70% of EDA that’s about verification that we’re really talking about here.
Forecasting the FPGA Future
The ball has dropped, the bubbly sipped, and the resolutions resolved. 2013 has ended, and before us we have a new year, a new universe of opportunity, and a crazy cauldron of activity in our beloved world of programmable logic. It’s time to throw down, gaze into the crystal ball, read the tea leaves, interpret the Tarot, and extrapolate the trend lines. Here, then, is our unflinching forecast for FPGAs in the months and years to come.
Before we fire up our forecast fest, we should nail down what we mean by “FPGA.” After all, the definition has been morphing, expanding, and shifting over the years, and even the companies with thousands of employees dedicated to nothing but making and selling FPGAs don’t seem to agree on the current meaning of the acronym. Ours will be simple - if it has a look-up-table (LUT) cell, it is an FPGA. (Yes, we hear the screams out there. Bear with us. It will all come out in the wash.)
Did Anything Happen?
2013 is coming to a close, and this is usually a time for reflecting on what’s happened in the past year and what’s going to happen in the coming year. The thing is, though, when I sit back and reflect, well, I don’t know; it just seems like 2013 was a quiet year for EDA.
So I took a couple of approaches to reviewing the year. One is to see what the Big Guys did and the other was to solicit some other opinions as to what’s in and what’s out.
Ben Heck, UVM Primer, and Printing with Metal
The year is drawing to a close, and the snow is falling, but the friday fun is just heatin' up. Our first guest is none other than Ben Heck from element14's wildly popular engineering television series "The Ben Heck Show". Ben gives us an exclusive preview of the next season of "The Ben Heck Show" and lets us in on how he got into this crazy business. Also this week, author Ray Salemi is here to light our way to a special place called UVM land. He's written a new book called "The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology" and he's here to break UVM down into its geeky bits and pieces. Finally, we close up this week's Fish Fry with a discussion about some innovative open source plans that could bring 3D metal printing right to your work bench. Saddle up, my friends, the fun is about to begin!
The propagation of unknown (X) states has become a more urgent issue with the move toward billion-gate SoC designs. The sheer complexity and the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final silicon. This article describes a methodology that enables design and verification engineers to focus on the X states that represent a real risk, and to set aside those that are artifacts of the design process. The goal is to reduce project time, particularly time spent in simulation, and overcome the limitations at both the RTL and gate level.
Billion-gate designs have millions of flip flops to initialize. Many of the IP blocks used in such designs also have their own initialization schemes.
Plays to its Base with AD14
The headline new feature for Altium’s newly released Altium Designer 14 (AD 14) is “Rigid-Flex Support.” True, rigid-flex is there, and it’s cool, but the headline might lead the casual reader to miss some very important changes that are happening at Altium. Altium has a new focus and a new mission these days. The Altium folks are going back to their roots, playing to their base, and trying to re-establish a strong partnership with the engineers the company was created to serve - the common, hard-working, in-the-trenches, everyday designers who are trying to create cool stuff but who don’t have the resources for the fantastically-expensive, enterprise-oriented PCB solutions from the likes of Mentor and Cadence.
For the past several years, Altium has been a bit like that genius ADD kid in the back of the classroom - full of brilliant ideas, but not at all focused on what is going on in class at the time. Altium has suffered from, if anything, an excess of forward-thinking vision - leading their customers with fascinating new design paradigm ideas and features, but failing them somewhat in delivering rock-solid implementation of the day-to-day, pedestrian PCB design capabilities needed for plain-old place-and-route. The rub on the street about Altium was that they were too focused on the flashy and not enough on fixing old bugs.
Can Cadence’s Voltus Make Us Less Pessimistic?
Many of the arts and skills developed throughout the ages have credited much of their inspiration to muses and patron saints and gods and spirits. These other-worldly beings provided both inspiration and guidance as the artisans built up a vast cultural legacy going back millennia.
So… if there’s a muse for engineering, who would it be? The thing about engineering is that free flights of fancy are often not permitted. We’re constrained by the possible, in stark contrast to experimental artists and even pure scientists. In fact, it’s worse than that: we have to make money. Usually for someone else. Which puts a further damper on things. Stuff has to work under a wide range of conditions, some predictable, some not.
The design and re-use productivity benefits of SystemC-based high-level-synthesis (HLS) are generally well understood. However, a major benefit of moving to this level of design that is rarely explored is improved verification turnaround and productivity.
Most system-on-chip (SoC) design flows employ SystemC transaction-level models (TLM) to create virtual prototypes. These virtual prototypes are used to verify the ever-increasing degree of software content. The utilization of SystemC models in the design flow forms an approach that Jim Ready, Cadence’s chief technology advisor for software and embedded systems, refers to as “software-driven SoC development”.
Cadence Talks About the Toughest Bits
Cadence recently announced a design flow for CoWoS 3D ICs. We’ve looked at some of the issues surrounding 3D IC technology before, but what we’ve looked at less are the specific ways designers will implement 3D ICs within their EDA flows.
So I talked with Cadence’s Brandon Wang to see what specific challenges they encountered and addressed in the flow that they announced. He listed three primary elements: heat, testing, and stress.