Cadence Talks About the Toughest Bits
Cadence recently announced a design flow for CoWoS 3D ICs. We’ve looked at some of the issues surrounding 3D IC technology before, but what we’ve looked at less are the specific ways designers will implement 3D ICs within their EDA flows.
So I talked with Cadence’s Brandon Wang to see what specific challenges they encountered and addressed in the flow that they announced. He listed three primary elements: heat, testing, and stress.
Do not pass go. Do not collect $200. Go directly to the power plane. Whether we like it or not, power integrity analysis is now a bigger (and messier) part of our PCB design process. In this week's Fish Fry, we get down to the bare metal of those pesky power planes with Brad Griffin of Cadence. Also this week, we check out a super cool new 3D printed robot (yes, you want one) and investigate what sets this little cutie apart from other humanoid robots.
Signal- and Power-Integrity Take Center Stage
Let’s face it, we went to school and studied logic design because we really didn’t want to deal with analog stuff. As digital designers, we prefer our signals to have nice discrete values and to stay out of those fuzzy grey areas. We may have even settled into a clean, orderly area of engineering like FPGA design - just to preserve a firewall between us and that nasty curvy stuff.
Then, of course, our arrogant “need for speed” brought us to things like multi-gigabit serial interfaces. Suddenly, what should have been a well-behaved sequence of zeroes and ones took on a suspicious likeness to those wavy analog lines we were trying to avoid in the first place. We justified it by pointing to the benefits of getting rid of all those unsightly parallel busses. Still, terms like “eye diagram” entered our vernacular - and the next thing you know, somebody was talking about signal integrity. Yuk!
Unraveling SADP Part 2
This is the second part in our two-part series on the SADP version of double-patterning. I’d make some crack about your brains having recovered after Part 1, but realistically, despite all my overdramatic whining, that wasn’t that bad. That was the easy part.
In the first part, we looked at fundamental SADP concepts. (If you haven’t read it and this is new to you, I highly recommend…) But in the interest of focusing on the basics, I took some liberties (which I noted) that we now need to address. Now we need to figure out how to create an actual mask. This is where things start to look more evil.
Happy Birthday to Us
Ten years ago, we had a vision - a vision of a new kind of trade publication: one that was completely digital; one that gave top-quality objective analysis and editorial on the electronics industry; one with a personality and a sense of humor that made professional engineering articles fun and interesting as well as informative; one staffed by people with firsthand experience in the engineering trenches and deep knowledge of the industry.
Then, we said, “Nah,” and created this one instead.
OK, kidding aside, this is our ten-year anniversary and we wanted to at least build a little digital bonfire and sit around it talking about the old days when we did three-micron tapeouts with actual tape, and when we put green magic marker around the edge of our software CDs in hopes of reducing the number of bugs. (Hey, if it was supposed to make CD music sound better, worth a try, right?)
Unhinged with Brian Fuller
Who said electronic engineering can't be funny? (Someone who has never read this publication!) In this week's Fish Fry, we check out a brand new online television show that that aims to bring the saucy style of late night television talk shows to our engineering community. My guest is Brian Fuller of Cadence Design Systems, and we chat about why Cadence decided to make a humorous engineering-based talk show and how they are going about the business of making EE fun.
Unraveling SADP – Part 1
What follows is something I enter into with great trepidation. Getting this… article thing… to a point where you can read it has involved more brain cell abuse than I inflicted upon myself during my entire college career. OK, it sort of feels like that, anyway.
We’re going to talk about double-patterning. Yeah, I know, we’ve talked about it before and it wasn’t so bad, was it? Ah, that’s because there isn’t just one double-patterning: there are two. Actually, there are more than two, but most of the other major variants don’t seem to be finding their way into production, so we’re going to ignore them. Denial being an awesome tool when used the right way.
The Designer's Perspective
Circuit reliability verification has become a crucial step in IC design. Reliability requirements are not only growing in all market segments, including automotive/transportation, medical, mobile/wireless, and consumer electronics, but the complexity of today’s circuits is presenting unprecedented verification challenges. To get these designs to market in a timely manner, while ensuring they will perform as designed, designers need automated circuit reliability solutions that can quickly and accurately analyze these complex designs. From the designer’s perspective, two critical factors in efficient reliability verification are: • the ability to understand the logic of the circuit • the ability to recognize specific circuit topologies (patterns) associated with circuit reliability
ARM, Fujitsu, and UMC Add Their Voices
We noted recently the slight hesitation taking place in the rush to FinFETs. Some folks are taking another look at FD-SOI as a way of extending planar technology in a more cost-effective manner than what FinFETs promise.
But there’s more to planar than just FD-SOI. Some time back we also surveyed a new approach to planar transistors being pioneered by newcomer SuVolta. At the time, our focus was on how the basic transistor was supposed to work and any proof points that existed then, which were few.
Findin' Them Buggers Fast
Maybe it's an itch that just won't go away. Maybe it's a daydream buster - Aw dang, I didn't think of that. Or, maybe it's a recurring nightmare that runs you ragged each and every night. Yep, we're talking about hardware-assisted verification. It ain't easy and nobody ever said it was going to be. In this week's Fish Fry my guest is Frank Schirrmeister from Cadence Design Systems. We chat about why hardware-assisted verification is on everybody’s mind these days, and what we can do to make our verification lives a whole bunch easier.
Which is Where Your Users Are
Sometime during the last twelve months at one of the typical industry conferences, I took a typical briefing. To us in the journalism world, a “briefing” is when a company sits down with an editor like me and tells a story. Their hope is that we will retell that story. Because if the story comes from their pen, it sounds like marketing; if it comes from our pen, it sounds like journalism, which gives it an extra air of legitimacy.
Of course, if you’re like me or my EE Journal colleagues, you probably take their story, invert it, fold it ten ways, look at that one pointy bit, and focus on that. It all comes out very different from the original (but hopefully the facts are correct).
Synopsys Announces a Sensor Subsystem
There’s a scramble afoot as sensor and silicon and software and system folks try to jockey over the best way to implement and integrate sensors into a broad range of devices. You’ve got:
- Folks making sensors
- Folks making micro-controllers that can run sensor-related software
- Folks integrating sensors and micro-controllers together
- Folks integrating multiple sensors together in a single package, possibly with a micro-controller as well
- System guys controlling sensors via the AP in an SoC
- System guys including a sensor hub of some sort in an SoC
With summer drawing to a close, what better time to journey to the land of EDA - where the C is synthesized, the constraints are random, and the living is easy. We talk with Brett Cline (Forte Design Systems) about what's hot in C Synthesis these days, and we also check in with Steve Kinney from Nimbic. Not sure what Nimbic does? You're in luck - we're gonna tell you.
Zuken Expands Scope and Reach
Most of us have heard of Zuken. They have always been one of the quiet companies who made PCB layout software - and who was not Mentor or Cadence. If we decided to upgrade our board design capabilities, they were on the list of suppliers we'd consider. Nothing about Zuken particularly grabbed our attention other than the assumption that they could help us bring some order to blank FR4 just as well as the next guy.
In Japan, however, Zuken was certainly not just one of the pack. In Japan, Zuken has had dominant market share for years. If you designed boards in Japan and used anything else, you just might be eyed with some suspicion. Zuken was founded in 1976 and has over a thousand employees worldwide, so they're hardly a new kid on the block, and they are a substantial EDA company by any measure. Being headquartered in Japan, however (and listed on the Tokyo Stock Exchange), they don't show up on radar quite the same way as most of the rest of the EDA industry.
Oski Discusses End-to-End Block Verification
Formal verification has had a rough go over the years. It came onto the scene with tons of promise, and that promise remains, to some extent, promise. It’s hard to argue against the possibility of taking a spec and a circuit, pushing a button, and watching while some tool provides proof that the circuit is correct.
And watching… and watching… and, well, yeah, that’s where the problems cropped up. Waiting for an answer to some of these problems, if not done carefully, can require suspended animation so that you can be reawakened in some future year or century when the calculation is complete.