It's the slow decline of December. We’re wrapping up our projects, toiling away in expense reports, and lining up our ducks for 2013. Speaking of lining up ducks, we’re looking into the future this week - the future of EDA. Where in the heck is the tool market headed next year? How will recent major mergers and acquisitions affect the design tool landscape? My guest is Mike Gianfagna from Atrenta and we’re gonna talk about all of this and more.
In the last decade we have seen the process of timing signoff become increasingly complex. Initial timing analyses at larger process nodes such as 180nm and 130nm were concerned mostly with operation at worst-case and best-case conditions. The distance between adjacent routing tracks was such that coupling capacitances were marginalized by ground and pin capacitance. Hence, engineers seldom looked at the potential issues associated with cross-coupling and noise effects. It was simply easier to add a small amount of margin than to analyze crosstalk.
Starting at 90nm, and even more prominently at 65nm, an increase in coupling capacitance due to narrower routing pitches and taller metal segment profiles resulted in crosstalk effects becoming a significant concern.
MEMS is 20 years behind ICs.
So says MEMS consultant Alyssa Fitzgerald of AMFitzgerald. A lot can happen in 20 years – and it could well be argued that MEMS doesn’t have 20 years to catch up. If it has a choice. And if it can even catch up completely.
The issue is the “one device, one process” component of Yole’s MEMS Law. This is something you would never see with ICs, especially in today’s fabless/foundry world. With ICs, the foundry has a process, it works a particular way, it has been thoroughly characterized twelve ways from Sunday, and those results have been incorporated into increasingly sophisticated models that EDA tools can use to predict with reasonable accuracy just what the results of a particular circuit will be.
Synopsys Upgrades HAPS
Verification and test have always faced a tricky paradox: How do you build equipment to test and verify the biggest, fastest devices ever created?
After all, it stands to reason that the tester has to be faster than the thing it’s testing, and the prototype has to be bigger than the thing it’s prototyping. It means that those folks have to always be running ahead of the fastest runners in order to handle the problem.
When prototyping large SoC designs, this issue has always been handled by throwing a wall of FPGAs at the problem. Even though this poses significant challenges with issues like design partitioning and mapping the design to an FPGA-friendly format, it has been the most effective method available for getting a usable prototype up and working.
The military has dealt with this for years. And first responders ran headlong into the issue with 9/11.
You have a localized entity – a police department, a platoon, Red Cross folks on the front line – and it has its way of communicating internally. But when it has to work with another group – the fire department or the police from another town or perhaps a platoon from a different branch of the service – then suddenly they have to figure out how to patch all of these things that work fine on their own into a cohesive whole, getting messages from one to the other without any of it getting lost in the jumble at the boundaries.
MIPS Technologies Acquired by Imagination Technologies
It’s the circle of life. The great wheel of existence. One door closes; another opens. The end of a chapter, the beginning of another. Pick your favorite metaphor—MIPS Technologies has been packed up and sold.
That’s actually pretty good news for MIPS’s 160-some employees, but it still feels like the end of an era to me. One of the darlings of the RISC computer era, and an innovator in computers, microprocessors, and business models, is now just a division within the larger company of Imagination Technologies.
Xilinx Discusses 20nm
The two big FPGA companies want to be sure that you know they’re ahead.
They always have. It isn’t because you really needed to know, or because one or the other of them being ahead at any given time had any long-term industry-shaping ramifications. It’s just that this myopic, tit-for-tat, red vs blue, Hatfield and McCoy, be-the-first-to-blink behavior is, according to recent economic research, the optimal solution for members of a symmetric pre-emptive duopoly.
Or, maybe both sides just really hate those other guys.
A few weeks ago, Altera announced their vision for FPGA technology on the upcoming 20nm node. Now, it’s Xilinx’s turn. Does this mean that Altera is 2 months ahead of Xilinx in the all-important “next process node”?
The next process node is coming faster and faster with every passing press release. This week we’re taking a closer look at the brand new 14nm test chip rolled out by Cadence, ARM, and IBM, and we’re looking into the new nanotube memory technology being developed by IMEC and Nantero. Speaking of breaking new ground, my guest this week is Brad Quinton (Tektronix) and we’re going to chat about the most recent developments in FPGA prototyping, what Brad sees as the biggest problems for FPGA prototyping today, and why embedded instrumentation can be more effective than physical instruments.
Embedded Instrumentation Boosts Boards to Emulator Status
FPGAs are clearly the go-to technology for prototyping large ASIC/SoC designs. Whether you’re custom-designing your own prototype, using an off-the-shelf prototyping board, or plunking down the really big bucks for a full-blown emulator, FPGAs are at the heart of the prototyping system. Their reprogrammability allows you to get hardware-speed performance out of your prototype orders of magnitude faster than simulation-based methods. If you’re trying to verify a complex SoC or write and debug software before the hardware is ready, there is really no option but an FPGA-based hardware prototype.
There are basically two options for FPGA-based prototyping - simple prototyping boards and emulators.
D2S Simulates for Mask Writing
A dozen or so years ago, chipmakers ran into an issue. Features on chips were getting too small to print, and fundamental changes in how they were being printed (ahem: EUV) were long delayed.
The problem is that you’re not supposed to be able to get good feature resolution for feature sizes too far below the wavelength of light used to expose the wafer. The smaller you go, the worse things get. And these days, we’re small.
The saving grace came in two forms. You might think of one as pre-distortion: if the end of a line is going to get shortened and rounded, then you use a mask that has the line slightly lengthened and fattened at the end so that it winds up closer to what you intended.
Where in the world will Fish Fry take us this week? First, we’re going to a take quick stroll by the most recent Raspberry Pi news, then it’s on over to some “Magic Finger” technology being developed by the Universities of Toronto and Alberta, and then we'll drive into EDA land with Bill Neifert (Carbon Design Systems- CTO). Bill is going to chat with me about Carbon Design Systems's recent collaboration with Samsung, how $4 million dollars in venture funding comes into play, and what exactly Carbon is going to do with all that cashola.
Mergers, Patents, and a New Family of FPGAs
The world of electronic design can change in the blink of an eye. Before you know it, things you thought were tried and true have flipped the script. This week we’re checking out why Synopsys decided to acquire emulation powerhouse Eve, how non-volatile memory companies Kilopass and Sidense are settling their patent skirmishes (or not), and how Microsemi is shaking up the FPGA market with their new SmartFusion2 family of FPGAs.
Coventor Brings In a New CTO
A number of years ago, Coventor created a program called SEMulator 3D. Its target usage was for developing MEMS processes and devices, MEMS devices traditionally having the unfortunate characteristic that a specific device typically required a specific process. Coventor refers to it as “virtual fabrication” since it can abstract and model the steps used to fabricate a MEMS wafer.
One of their customers was IBM, and one of the people at IBM working with the tool thought that it would be useful for silicon processes as well. After all, some details and occasional strange materials aside, silicon circuits and MEMS chips are made the same way.
How many of you have gotten lost in your own corporate office building? Maybe it was your first week on the job? As hard as it is for us to navigate our own buildings, can you imagine what it's like for emergency responders? In this week’s Fish Fry we check out a new real-time 3D mapping prototype being developed by MIT and examine how it could revolutionize the way we navigate the world around us. Also this week, I interview Steve Yang (President and Founder - ICScape). Steve and I chat about how ICScape can help your timing closure problems, what their tool suite looks like, and what’s ahead for this new EDA startup from China.
Sometimes it feels like we’re just inching along toward innovation. Sometimes it feels like we’re flying by the seat of our pants toward the future without a seatbelt in sight. This week we’re talking about Intel’s long-range plans for a 5nm process node, why ESL should be playing a big role in your next low power design, and even why the cool kids aren't using discrete components for power supplies anymore.