Shifting Left

Designing Code, Breaking Code, and the Verification in Between

by Amelia Dalton

Like the venerable Kenny Rogers once said, “You have to know when to hold ‘em, know when to fold ‘em…” In the verification game, much is the same. You have to know how to make the code, and you have to know how to break it. In this week’s Fish Fry, David Hsu (Synopsys) joins us to discuss the challenges of static verification and formal verification, how to “shift left”, and how to make code just to break it. Also this week, we investigate how hierarchical timing analysis may solve your sign-off timing troubles once and and for all.  Read More


latest news

September 23, 2014

Synopsys Unveils Verification Continuum to Enable Next Wave of Industry Innovation in Software Bring-Up for Complex SoCs

September 22, 2014

Users Cite 10 Percent Smaller Design Sizes with Latest Releases of Synopsys' Design Compiler

Mentor Graphics Delivers Commercial Mentor Embedded Linux Platform and Graphics Enablement for AMD Embedded G-Series and R-Series Devices

Mentor Graphics and Lumerical Unify Optical Design and Simulation Flow

September 19, 2014

Leadcore Achieves First-Pass Silicon Success with DesignWare MIPI IP in Smartphone Application Processor SoC

September 18, 2014

Keysight Technologies’ UXM Wireless Test Set Expands Functional Test Capabilities, Delivers Greater RF Design Confidence

Synopsys' New DesignWare MIPI D-PHY Cuts Area and Power by 50 Percent

September 17, 2014

Cavium Standardizes on Synopsys' IC Compiler for High-performance Processor-based SoC Designs

Real Intent to Exhibit at First DVCon India

Synopsys' New MIPI C-PHY Verification IP Accelerates Adoption of MIPI Alliance's Physical Layer Specifications

September 16, 2014

Major Taiwanese DMS Company Pegatron Establishes New PCB Design Flow through Technical Cooperation with Zuken

Saelig Debuts Packet-Master 'USB Power Delivery' Testers

September 15, 2014

Elmos Selects Synopsys' Custom and Digital Design Solutions

September 12, 2014

Wipro Accelerates SoC Verification with Synopsys Verification IP Portfolio

September 10, 2014

Synopsys Introduces RSoft OptSim Circuit to Automate Design of Next-Generation Photonic Integrated Circuits (PICs)

EDA News Archive

Go-Fast FPGA Design

Helpful Hot-Rodding Hints

by Kevin Morris

Going Vertical

Ecosystem for Interposer-based Design?

by Kevin Morris

On The Hunt: Part One

HLS and Sub-atomic Particle Jitter

by Amelia Dalton

Optimization Moves Up a Level

Mentor’s RealTime Designer Rises to RTL

by Bryon Moyer

A Horse of a Different Color

Advanced vs. Established Process Geometries

by Amelia Dalton

EDA Article Archive

 

Editors' Blog

Faster Extraction from Cadence

posted by Bryon Moyer

Cadence has upgraded their parasitic extraction tools for the 16-nm node. (28-Aug)

Planning PCB, Package, and Die Together

posted by Bryon Moyer

Cadence’s OrbitIO tries to tie together disparate tools and inefficient ways of planning pinouts. (31-Jul)

Intelligent VIP

posted by Bryon Moyer

Arrow Devices focuses on building semantics into their VIP for a higher level of abstraction. (23-Jul)

Improved FPGA Tool Results

posted by Bryon Moyer

Plunify tries to get the best out of FPGA design tools (21-Jul)

Synopsys’s IP Initiative

posted by Bryon Moyer

Synopsys is taking a holistic view of SoC design using IP, including hardware and software elements. (17-Jun)

EDA Editors' Blog Archive

forum

IoT Standards

Posted on 09/22/14 at 5:19 PM by bmoyer

bmoyer
Thanks for the link, Will. I'll look into it.

Tiny Diamonds

Posted on 09/22/14 at 9:50 AM by bmoyer

bmoyer
What do you think about using ultra-nano-crystalline diamond as an actuator?

Differentiation versus Diversity

Posted on 09/18/14 at 10:10 PM by TileGuy

TileGuy
Hi Jim, nice to see your very positive comments about Tilera’s architecture and performance achievements. And we've got over 100 designs at companies like Cisco, Brocade, ZTE, Checkpoint who agree with that. But it’s worth correcting a couple statement…

EDA Forum Archive

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