Spaghetti versus ISO 26262

Are You Ready for Tomorrow?

by Dick Selwood

There are times when you shouldn't really think too deeply about things. Last week I was driving along the motorway from London to Winchester. While accelerating to overtake, I saw the engine pass through 4,000 rpm, and I wondered about each piston moving from stationary at top dead centre to stationary at bottom dead centre and then back to top dead centre 50 times a second. (Geeky? Moi?) Sadly, I can't perform in my head the sum that would calculate the speed at which each piston was moving at its fastest, but it must be pretty speedy, and that cycle of movement would be putting all sorts of stresses on all sorts of metal parts. I eased my mental stress by consoling myself that, at least in my 15-year-old Golf, there wasn't software running on silicon to control the engine.

So I didn't have to worry that the software could be like that in the Toyotas that may have suffered unintended acceleration. There has been no resolution on whether the software caused the issue. The evidence of software guru Michael Barr was so damning that, while he couldn't say that the software caused the incident, he had the Toyota lawyers worried. Add to this the way in which the opposing legal team were being successful in throwing dust into the eyes of the jury and sowing doubt into their minds, and it is clear why Toyota settled out of court.  Read More


latest news

November 25, 2014

Symtavision extends collaboration with Lauterbach to significantly improve tool integration with TRACE32®

November 24, 2014

Invionics Launches Platform that Speeds In-house EDA Tool Development, Solves Critical Design Flow Bottlenecks

Keysight Technologies Demonstrates LTE-Advanced 450 Mbps End-to-End IP Data Throughput with UXM Wireless Test Set

November 19, 2014

Synopsys Expands IP Accelerated Initiative with New DesignWare IP Prototyping Kits for 10 Interface Protocols

November 18, 2014

Oticon Standardizes on Synopsys' Design Compiler Graphical

November 17, 2014

Synopsys' IC Validator Adopted by Plastic Logic for Physical Verification of Advanced Displays

November 12, 2014

Plunify’s InTime Design Optimization Software Supports Altera FPGAs and SoCs

Tektronix Releases First Test Solution for MIPI M-PHY® Specification v3.1

Altium and element14 Partner to Distribute New PCB Design Tool CircuitStudio

November 11, 2014

Nitero Achieves First-Pass Silicon Success for Industry's First Mobile 60GHz SoC Using Synopsys DesignWare IP for PCI Express and Tools

November 10, 2014

Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development

Latest Release of Synopsys' CODE V Optimizes Optical Design Performance for Cost-Effective Manufacturing

Digi-Key Expands Portfolio of EDA Software Tools

November 07, 2014

ProPlus Design Solutions Strengthens Leadership Position with Re-Innovated, Long-Lived BSIMProPlus SPICE Modeling Platform

November 06, 2014

Keysight Technologies Introduces Oscilloscope Probes for High-Voltage Signal Measurements

EDA News Archive

Finding the Right Prototype

Carbon Design Systems Announces the Carbon System Exchange

by Bryon Moyer

Over the FR4 and Through the Woods

To Grandma's PCB We Go

by Amelia Dalton

Constraining Light

Or, How the Heck Do I Design a Photonic Circuit?

by Bryon Moyer

First Responder Robots and Virtual Prototypes

Carbon’s New Virtual Prototype Portal and UDG’s New Smart Robot

by Amelia Dalton

Expanding EDA

Newer Tools Let You Do More than Just Electronics

by Bryon Moyer

EDA Article Archive

 

Editors' Blog

Verdi: Not Just for Debug Anymore

posted by Bryon Moyer

Synopsys is leveraging Verdi for things that aren’t debug. Like verification planning. (Yesterday)

If This Is a Conference, then It Must Be November

posted by Bryon Moyer

A quick look at some of the events I’ll be attending over the next few weeks. (24-Oct)

Faster Extraction from Cadence

posted by Bryon Moyer

Cadence has upgraded their parasitic extraction tools for the 16-nm node. (28-Aug)

Planning PCB, Package, and Die Together

posted by Bryon Moyer

Cadence’s OrbitIO tries to tie together disparate tools and inefficient ways of planning pinouts. (31-Jul)

Intelligent VIP

posted by Bryon Moyer

Arrow Devices focuses on building semantics into their VIP for a higher level of abstraction. (23-Jul)

EDA Editors' Blog Archive

forum

Spaghetti versus ISO 26262

Posted on 11/25/14 at 9:25 AM by Dick Selwood

Dick Selwood
Are you working in automotive? Are you working to ISO 26262? Is there anything you would like to share?

Finding the Right Prototype

Posted on 11/24/14 at 9:38 AM by bmoyer

bmoyer
What do you think about these virtual system prototypes and how to find them?

A Sale of Thirty-Two Bitties

Posted on 11/24/14 at 9:34 AM by Jim Turley

Jim Turley
How about a series of low-end x86 chips for embedded systems? Would that fly?

Back in Ye Olden Tymes, AMD and Intel used to make a bunch of embedded x86 processors, but they both canceled them after a few years. That kind of burned a lot of embedded d…

EDA Forum Archive

subscribe to our eda newsletter



On Demand

Power-Aware Verification in Mixed-Signal Simulation

Assertion-Based Emulation Using Veloce

SoC Interconnect Verification

The Vault

OrCAD Now! Signal Integrity Presentation

OrCAD Now – PSpice

Speed IP Bring-up and SoC Validation with HAPS-DX

Synopsys ProtoCompiler for RTL Debug with HAPS Systems

What is Electrically Aware Design?

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

PADS VX: Redefining Productivity

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

Vivado In-System Debug

Design Control, Data & Comparison with PADS Design Archive

Protium Rapid Prototyping Platform

Static Timing Analysis and Constraint Validation

Scripted Flows in Vivado Design Suite

Vivado Design Suite: Integrated Design Environment

Rigid-Flex and Embedded Components

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

Cadence Low Power Solution - RTL to GDSII Low Power Design

Routing Interfaces Quickly & Efficiently on PCBs

EDA On Demand Archive


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register