MIPS Plants a New Family Tree
“Aptiv” Line of Processors: the Start of a New Generation
Blame BMW. Or maybe Sears, Roebuck & Co. The trend of classifying all your products into clearly defined low, middle, and high ranges has now extended its grasp to MIPS Technologies.
Carmakers figured out a long time ago that it would help sell cars if consumers could keep all the confusing model numbers straight. Thus, General Motors had its Chevrolet brand (low end), its Buicks (midrange), and its Cadillacs (high end). That branding strategy served the company quite well, even when all three cars were actually the same vehicle with different hood ornaments. Read More
latest news
May 18, 2012
May 16, 2012
EVE Unveils 10-Gigabit Ethernet Validation Platform
Carbon Design Systems Unveils Off-the-Shelf Performance Analysis for ARM Cortex-A Processors
EVE Adds New Applications for Leading SoC Emulation Platform Environment
IC Manage Releases 4th Annual Global Design Management Survey Results
May 15, 2012
Forte’s SystemC High-Level Synthesis Licensed by HighIP Design Company
Cadence Introduces New NVM Express IP Solutions for Solid State Storage Applications
May 14, 2012
Sigrity Introduces XcitePI Chip IO Interconnect Model Extraction and Assessment Tool
Satin Technologies to Introduce Automated Design Monitoring at DAC 2012
X-FAB Joins the IPL Alliance and Announces iPDK Availability
The Process of Process Tracking
Satin Attempts to Corral a Recalcitrant Beast
Springtime in the SoC
Audio IP, Static Analysis and Board Member Switch-a-roo
An EDA Foil Hat
iROC Attacks Cosmic Attacks
Power When You Need It
Aldec Harnesses Massive Server Capacity
Editors' Blog
Powering Up Power Analysis
Apache addresses power analysis of 3D ICs and sub-20-nm behemoth chips. (8-May)
FPGA Prototype Debug Access
Synopsys tries to ease the tradeoff between trace capture speed and FPGA resource utilization. (7-May)
High-Sigma Simulations
Solido is offering a way to achieve high-sigma confidence on high-variation processes without requiring billions of simulations. (4-May)
Emulator in the Cloud
So you need to test out real software against your new OneChip2RuleThemAll SoC. But you blew too much of your funding on that all-hands Christmas bash in Cabo. Whatcha gonna do? (3-May)
New Emulator Help
Mentor upgrades to Veloce2 and adds a virtual peripheral capability. (1-May)
forum
Wirelessly Going Where No Man Has Gone Before
Posted on 05/18/12 at 4:19 PM by jyeh
Ready, Set, Embed!
Posted on 05/18/12 at 3:35 PM by amelia
Springtime in the SoC
Posted on 05/17/12 at 11:25 AM by Parag
This will be auto temperature and humidity controller for the farms. …
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Integrating High-Level Synthesis Designs into SoCs with Less Effort and Risk
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Methods and Tools for Bring-Up and Debug of an FPGA-Based ASIC Prototype
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High-Reliability in FPGA Design - SEU Mitigation
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IP and Process Solutions for Energy-efficient PMICs
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Teradici Success Story
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FPGA Design Methods for Fast Turnaround
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