Ecosystem for Interposer-based Design?
We’ve talked a lot lately in these pages about the impending demise of Moore’s Law. Consensus is that, somewhere around the half-century mark, one of the most astounding prophecies in human history will have finally run its course. Next year, we’ll have a round of FinFET devices that will be so exotic and expensive that only a handful of companies will be able to use them. In the decade that follows, we may or may not reach 10nm and 7nm production - using either esoteric unlikelies like EUV or extreme-brute-force multi-patterning techniques - to solve just some of the multitude of barriers to continued downscaling.
Sci-fi techniques like carbon nanotubes, graphene-based devices, quantum computing, and that other-one-you-read-about are so far from production practicality that we may not see any of them in widespread use in our lifetimes. While incredible research shows great promise for many of these ideas, they are all back in the silicon-equivalent of the early 1960s in their evolution. The time and engineering it will take them to catch up with and eventually surpass what we can do with silicon today is substantial.
A Hot DATE in Dresden
The Dresden conference centre was designed to represent a stark modern contrast to the restored Baroque buildings of the old town of Dresden. For some reason, the architects decided to build a curved building with one floor on a slope, cutting through other, flat, floors. The entrance is up a long flight of stairs, exposed to the wind and rain blowing across the river Elbe. The conference rooms are all provided with wonderful glass walls overlooking the river, which have to be blacked out if you want to be able to see the information projected onto the screen.
However, it is the the main conference venue for Silicon Saxony, a “cluster” of high tech companies ranging from semiconductor manufacturers Global Foundries and Infineon to a wide range of supporting and related businesses: over 300 companies are part of the network. And it is where, in alternate years, the academic community engaged in EDA make their spring pilgrimage to the DATE Conference.
The Dark Side of Reporting Features
Do you like to be watched while you work?
Most people don’t. There’s this fine line between making sure that stakeholders know about your progress on a project and having those stakeholders all up in your business all the time. The latter is micromanagement, and no one likes that.
More and more EDA tools are being provisioned with management and reporting features. These make it easier for you as a designer to let your supervisor or project manager know what you’ve accomplished and what remains – and you spend less time writing up those annoying status reports.
Part 2 - Mentor Xpedition
Mentor Graphics is number one in PCB design tools. They want me to tell you that. They want me to tell you that - even after reading about my disdain for marketing the market share of your product. So - there ya go. They’re number one. Why does this matter? Well, they rightfully point out that nobody ever got fired for buying the leading tool, and that EDA can be a fickle business. If an EDA tool is number one (they observe), the company selling it probably cares about it deeply and will want to go the distance to support you and make you happy. Point taken.
However, since we’re all engineers here, the thing that matters the most - by FAR - is whether the tool is robust and reliable in helping you get your engineering job done. In this case - that means helping you be as productive as possible designing the heck out of your PCB. Luckily, besides being number one, Mentor has done a very respectable job of that as well. Now, however, they think that’s not enough. They’re launching a big ’ol ambitious program to upgrade their PCB design suite - in a clear effort to fend off the similarly ambitious competitors (Cadence, Zuken, Altium, et al) who are coming full-tilt right at them.
Part 1 - Cadence Allegro TimingVision
They say timing is everything, and when designing digital electronics, “they” are absolutely correct. Unless we can get the timing right on every path in our project, we’re going nowhere fast. Timing closure runs the gamut of our engineering tasks - from the inside of our FPGAs through our boards and out into the world.
With the proliferation of high-speed interfaces into common standards like DDR, PCI and others, even “normal” PCB design can involve complex timing issues, and resolving all of them at once can be a bit like squeezing a balloon. We have paths that need to meet minimum or maximum delay specifications, groups of paths that must be equal length, differential pairs that must be routed together, and phase alignment corrections that must be applied. And, all of these need to be handled during PCB routing - at the same time that we’re struggling with things like getting from point A to point B, minimizing the number of vias and layers, navigating our way out of complex BGA pin fields, and applying our sense of aesthetics to our work.
More Than Superconductors?
Last year, I delved a little into the world of superconductors and their bizarre circuits. In poking about afterwards, I ran across something called an “ultraconductor.” I wondered if this was a brand of superconductor – it wasn’t. So what is this thing?
Turns out, it’s not just one thing. I found two threads to pull, and they were different. One led to an organic approach – which would sound pretty danged interesting – but it is not being actively pursued at the moment. (I’m not sure why; for now it’s an academic question, and I’ll tackle it if we ever come back to it.)
The other thread related to some work done at the Los Alamos National Labs (LANL). One Dr. James Maxwell was leading a project to improve conductance beyond what metal alloys could provide.
Fish Fry Takes on DesignCon 2014
The lights: Fluorescent. The carpet: Padded. The lanes: Routed. Where in the world could Fish Fry be? DesignCon 2014, of course. In this special DesignCon episode of Fish Fry, we launch ourselves into the multi-faceted world of electronic design with a couple of interesting interviews. My first guest is none other than Kilopass CEO Charlie Cheng. Charlie and I get down to the nuts and bolts of non-volatile memory, and Charlie gives me his take on where he thinks the technology is headed over the next few years. Next, I chat with Mark Toth (CadSoft) about CadSoft's ubiquitous EAGLE PCB Design Software, and I get the inside scoop on the results of their recent PCB design survey.
Plays to its Base with AD14
The headline new feature for Altium’s newly released Altium Designer 14 (AD 14) is “Rigid-Flex Support.” True, rigid-flex is there, and it’s cool, but the headline might lead the casual reader to miss some very important changes that are happening at Altium. Altium has a new focus and a new mission these days. The Altium folks are going back to their roots, playing to their base, and trying to re-establish a strong partnership with the engineers the company was created to serve - the common, hard-working, in-the-trenches, everyday designers who are trying to create cool stuff but who don’t have the resources for the fantastically-expensive, enterprise-oriented PCB solutions from the likes of Mentor and Cadence.
For the past several years, Altium has been a bit like that genius ADD kid in the back of the classroom - full of brilliant ideas, but not at all focused on what is going on in class at the time. Altium has suffered from, if anything, an excess of forward-thinking vision - leading their customers with fascinating new design paradigm ideas and features, but failing them somewhat in delivering rock-solid implementation of the day-to-day, pedestrian PCB design capabilities needed for plain-old place-and-route. The rub on the street about Altium was that they were too focused on the flashy and not enough on fixing old bugs.
Intelligent Testing for Software
Everyone knows that, when developing software, you are going to have to spend a lot of time testing: identifying the bugs that are causing the software to fail, correcting the bugs, and then testing again. This phase has been estimated to take as much as 70% of the software development time for an embedded product. Last week, I attended a conference on intelligent testing, expecting to hear from a range of speakers on how their tools, research, or consultancy could improve or shorten the testing cycle. And, indeed, there was some discussion of specific tools – as we will see later. But two papers were different. The most pertinent was by Jim Thomas, a consultant who has a background of test tool development.
Signal- and Power-Integrity Take Center Stage
Let’s face it, we went to school and studied logic design because we really didn’t want to deal with analog stuff. As digital designers, we prefer our signals to have nice discrete values and to stay out of those fuzzy grey areas. We may have even settled into a clean, orderly area of engineering like FPGA design - just to preserve a firewall between us and that nasty curvy stuff.
Then, of course, our arrogant “need for speed” brought us to things like multi-gigabit serial interfaces. Suddenly, what should have been a well-behaved sequence of zeroes and ones took on a suspicious likeness to those wavy analog lines we were trying to avoid in the first place. We justified it by pointing to the benefits of getting rid of all those unsightly parallel busses. Still, terms like “eye diagram” entered our vernacular - and the next thing you know, somebody was talking about signal integrity. Yuk!
Zuken Expands Scope and Reach
Most of us have heard of Zuken. They have always been one of the quiet companies who made PCB layout software - and who was not Mentor or Cadence. If we decided to upgrade our board design capabilities, they were on the list of suppliers we'd consider. Nothing about Zuken particularly grabbed our attention other than the assumption that they could help us bring some order to blank FR4 just as well as the next guy.
In Japan, however, Zuken was certainly not just one of the pack. In Japan, Zuken has had dominant market share for years. If you designed boards in Japan and used anything else, you just might be eyed with some suspicion. Zuken was founded in 1976 and has over a thousand employees worldwide, so they're hardly a new kid on the block, and they are a substantial EDA company by any measure. Being headquartered in Japan, however (and listed on the Tokyo Stock Exchange), they don't show up on radar quite the same way as most of the rest of the EDA industry.
“Chips” are So Passé
The term “SoC” has been in use for about two decades now. Systems-on-Chip were a great idea, of course. Over the years, as we marched forward with Moore’s Law, steadily reducing the number of chips in our systems, we could see the finish line ahead of us somewhere. Eventually, we reasoned, this increased integration would allow us to put our entire system on a single chip. Sure enough, for many of us, our design elements dwindled from dozens to single digits, and ultimately approached that magical vanishing point - unity - one chip to rule them all.
Eventually, we rationalized victory. The marketers amongst us were all too excited to be the first to proclaim, “We are doing System on Chip!” Banners were waved and bandwagons opened their admission gates. We were no longer simply Chip designers, we were SoC designers! Strike up the band! The future is here! We are now in the SoC business!
or...How to Build a Desktop Personal Supercomputer
Foreword by Kevin Morris
Have you noticed that there is no Moore’s Law for circuit boards? Sure, we have seen some gradual improvement in PCB technology over the past couple of decades, but we’re still pushing FR4 around pretty much the same way we always have, and the PCB is now a huge limiting factor in our ability to miniaturize our systems and make them more reliable.
Is it getting to be time to ditch the FR4?
Bob Conn is a fascinating guy – what many of us in engineering would think of as a “renaissance man.” We are excited to present the first in a series of articles by Bob about silicon circuit boards (SiCBs). Bob will take us through the practicalities of using SiCBs in the current world and give us insight in to how SiCBs may evolve as viable solutions for an increasingly large segment of our design work.
A Conversation About Mentor’s FloTHERM XT Raises the Question
Electronics power density is approaching that of a nuclear reactor core. But don’t worry – it’s still an order of magnitude less than that of a rocket nozzle.
This was the eye-opening “got your attention?” snippet in a presentation launching Mentor’s new FloTHERM XT tool.
The idea of this particular tool is to make life easier for PCB and system designers as they manage heat by bringing together EDA and MDA (Mechanical Design Automation) data early in the conceptual stage of a design to allow earlier, faster thermal simulation.
New DRAM Interfaces Keep Memory Buses Humming
A pair of new DRAM interfaces broke cover recently, and both promise to make engineers’ lives tougher – no, wait, easier! Sorry. Easier because the new interfaces make memory faster and more power-efficient (both good things), but tougher because it’ll be harder to decide which one you want. And they’re definitely mutually exclusive.
One interface comes from the Hybrid Memory Cube Consortium, a nonprofit group of DRAM makers and DRAM users (that’s a large group) that collectively work on defining how hybrid memory cubes should work. The other comes from Rambus, the decidedly for-profit company that makes its business developing and licensing interface-related IP.