posted by Bryon Moyer
The latest, greatest mobile standards appear to be beastly affairs. Added to the old ones, and the number of algorithms that a poor cellphone – even a smart one – has to manage becomes pretty daunting.
And features like MIMO – various permutations and combinations of multiple antennae on the sending and receiving sides – make for an array of possible algorithms that CEVA says can only be managed through a software approach. That is, you load the software you need for the algorithm required at the moment rather than hard-code every possible variant, which would simply take too much silicon.
CEVA attacks this market with their XC architecture, and they recently beefed it up by announcing a multicore version. “OK, big deal,” you might say. “I had one core, now I can have more than one. I could do that before by instantiating more than one.”
Yes and no. Going truly multicore means one more huge addition to the architecture, most of which operates in the background: cache coherency. So even if that was all they had done, that’s a lot of work in its own right.
But they appear to have gone beyond that, adding packet management and scheduling hardware, along with design tools that understands higher-level concepts like queues and buffers. And frankly, at least conceptually, this starts to look a lot like a Cavium OCTEON chip, only with DSPs instead of RISC CPUs.
But, of course, this is IP, not hard silicon (although they have emulation boards). So you can configure things any way you want – including homogeneous and heterogeneous architectures, the latter blending DSPs and CPUs if desired.
They’ve also added floating point support; they point to the MIMO algorithms as a particularly compelling reason to move beyond fixed-point.
So it’s a larger leap than just adding another core or two. You can see more of the speeds and feeds in their release.
posted by Bryon Moyer
An interesting development was announced yesterday in the photonics world. In what appears to be a first of its kind, at least commercially, Skorpios announced a monolithic tunable laser – CMOS and 3/5 bits on the same chip. This eliminates the need to have the circuitry on one chip and then drive that into a separate chip that does the lasing, with obvious integration and efficiency benefits.
Skorpios does custom photonic work for its strategic investors, and in doing this process development, they have put together what amount to photonic standard cells; they talk about opening up an ASIC-like capability for integrated photonics. While it’s possible they could consider licensing out these cells in the future, that’s not their plan now, so for the most part, the cell capability benefits them internally as they take on custom projects and deliver monolithic results.
The real question, though, is what they did to make this feasible and commercially viable. And detailed answers on that are not forthcoming yet. More disclosure is planned, and I hope to be able to talk more about how they got their results at that time.
You can get more on the current level of released information from their press release.
posted by Bryon Moyer
One of the things about CNTs acting as transistors is that the current flowing through them has to get into and out of the CNT from some other substance – typically metal. That junction, as it turns out, can have significant resistance. According to a paper done by a team from Georgia Tech and MIT (Songkil Kim et al), for a single-walled CNT (SWCNT) to connect to metal, there’s a quantum limit of around 65 kΩ.
Multi-walled CNTs (MWCNTs) can provide much lower-resistance connections, but how low depends on how you do it. Sputtering or evaporation only gets you to 3-4 kΩ best case, with no contamination. You can get as low as 700 Ω using TEM-AFM and nano-manipulation + joule heating, but this isn’t a viable commercial process.
The team used E-beam-induced deposition (EBID), which is essentially a localized CVD, where the gas is decomposed with great control using an electron beam. The overall process consists of first graphitizing amorphous carbon and then forming the connections.
Annealing amorphous carbon into graphite proved something of a challenge. They tried using a current to create joule heating, but it was tough to control: as the annealing progressed, the resistance went down, driving up the current and leading to runaway that could cause damage. So they went to an oven instead. They had to keep the temperature at 350 °C, the temperature at which graphitization starts, to keep the CNTs from oxidizing at higher temperatures.
In order to connect the multiple walls that were formed to metal, they directed the e-beam near the connection point. At first they aimed slightly short of the connection, using the backscatter to connect the inner walls – kind of like a basketball layup. Then they focused directly on the connection to finish it up.
This was followed up by an anneal.
The results were as follows:
- Before making the contact, resistance was in the GΩ range.
- If only the outer wall was connected, they got a 3.8-kΩ connection.
- The EBID process alone brought the resistance from GΩ to 300 kΩ.
- A 10-minute anneal at 350 °C brought the resistance down to 1.4 kΩ.
- A further 20-25 minutes of annealing brought the resistance all the way down to 116 Ω.
Note that, to the best of my knowledge, this process was not used by the team that created the first CNT sub-systems recently reported at ISSCC.
You can find out more details in the published paper, but note that it’s behind a paywall.